Analysis & Synthesis report for sirena
Tue May 17 08:57:41 2011
Quartus II Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Registers Removed During Synthesis
 10. Removed Registers Triggering Further Register Optimizations
 11. General Register Statistics
 12. Multiplexer Restructuring Statistics (Restructuring Performed)
 13. Source assignments for frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram
 14. Source assignments for frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram
 15. Source assignments for frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram
 16. Source assignments for frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram
 17. Source assignments for frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram
 18. Source assignments for message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram
 19. Parameter Settings for User Entity Instance: Top-level Entity: |sirena
 20. Parameter Settings for User Entity Instance: pll96:pll0|altpll:altpll_component
 21. Parameter Settings for User Entity Instance: frontend:front
 22. Parameter Settings for User Entity Instance: frontend:front|spi_slave:arm
 23. Parameter Settings for User Entity Instance: frontend:front|spi_slave:arm|spi_timeout:tout
 24. Parameter Settings for User Entity Instance: frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component
 25. Parameter Settings for User Entity Instance: frontend:front|conf_reg:spide_reg
 26. Parameter Settings for User Entity Instance: frontend:front|conf_reg:spide_reg|stat_reg:rback|readback_buffer:b
 27. Parameter Settings for User Entity Instance: frontend:front|cntl_reg:master_conf
 28. Parameter Settings for User Entity Instance: frontend:front|cntl_reg:master_conf|stat_reg:rback|readback_buffer:b
 29. Parameter Settings for User Entity Instance: frontend:front|cntr_reg:master_clock|stat_reg:rback|readback_buffer:b
 30. Parameter Settings for User Entity Instance: frontend:front|stat_reg:master_stat|readback_buffer:b
 31. Parameter Settings for User Entity Instance: frontend:front|error_reg:master_errc|stat_reg:rback|readback_buffer:b
 32. Parameter Settings for User Entity Instance: frontend:front|conf_reg:hksizereg
 33. Parameter Settings for User Entity Instance: frontend:front|conf_reg:hksizereg|stat_reg:rback|readback_buffer:b
 34. Parameter Settings for User Entity Instance: frontend:front|conf_reg:hkmaskreg
 35. Parameter Settings for User Entity Instance: frontend:front|conf_reg:hkmaskreg|stat_reg:rback|readback_buffer:b
 36. Parameter Settings for User Entity Instance: frontend:front|conf_reg:hkhdrvreg
 37. Parameter Settings for User Entity Instance: frontend:front|conf_reg:hkhdrvreg|stat_reg:rback|readback_buffer:b
 38. Parameter Settings for User Entity Instance: frontend:front|packetfifo:hkfifo
 39. Parameter Settings for User Entity Instance: frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component
 40. Parameter Settings for User Entity Instance: frontend:front|packetfifo:f1
 41. Parameter Settings for User Entity Instance: frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component
 42. Parameter Settings for User Entity Instance: frontend:front|packetfifo:f2
 43. Parameter Settings for User Entity Instance: frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component
 44. Parameter Settings for User Entity Instance: frontend:front|packetfifo:f3
 45. Parameter Settings for User Entity Instance: frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component
 46. Parameter Settings for User Entity Instance: message:msg
 47. Parameter Settings for User Entity Instance: message:msg|crc_byte:crc_rx
 48. Parameter Settings for User Entity Instance: message:msg|crc_byte:crc_rx|crc:crc
 49. Parameter Settings for User Entity Instance: message:msg|crc_byte:crc_tx
 50. Parameter Settings for User Entity Instance: message:msg|crc_byte:crc_tx|crc:crc
 51. Parameter Settings for User Entity Instance: message:msg|uart:uart
 52. Parameter Settings for User Entity Instance: message:msg|uart:uart|pps:rxpps|pps_rx:cx1
 53. Parameter Settings for User Entity Instance: message:msg|uart:uart|pps:rxpps|pps_rx:cx2
 54. Parameter Settings for User Entity Instance: message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component
 55. Parameter Settings for User Entity Instance: cntr_array:cntrs
 56. Parameter Settings for User Entity Instance: cntr_array:cntrs|cntr_reg:cntr[1].c|stat_reg:rback|readback_buffer:b
 57. Parameter Settings for User Entity Instance: cntr_array:cntrs|cntr_reg:cntr[2].c|stat_reg:rback|readback_buffer:b
 58. Parameter Settings for User Entity Instance: cntr_array:cntrs|cntr_reg:cntr[3].c|stat_reg:rback|readback_buffer:b
 59. Parameter Settings for User Entity Instance: cntr_array:cntrs|cntr_reg:cntr[4].c|stat_reg:rback|readback_buffer:b
 60. Parameter Settings for User Entity Instance: cntr_array:cntrs|cntr_reg:cntr[5].c|stat_reg:rback|readback_buffer:b
 61. Parameter Settings for User Entity Instance: cntr_array:cntrs|cntr_reg:cntr[6].c|stat_reg:rback|readback_buffer:b
 62. Parameter Settings for User Entity Instance: conf_reg:apid_reg
 63. Parameter Settings for User Entity Instance: conf_reg:apid_reg|stat_reg:rback|readback_buffer:b
 64. Parameter Settings for User Entity Instance: stat_reg:len_reg|readback_buffer:b
 65. Parameter Settings for User Entity Instance: stat_reg:stat_reg|readback_buffer:b
 66. Parameter Settings for User Entity Instance: memory:mem
 67. altpll Parameter Settings by Entity Instance
 68. scfifo Parameter Settings by Entity Instance
 69. Port Connectivity Checks: "stat_reg:stat_reg"
 70. Port Connectivity Checks: "cntr_array:cntrs|cntr_reg:cntr[6].c"
 71. Port Connectivity Checks: "cntr_array:cntrs|cntr_reg:cntr[5].c"
 72. Port Connectivity Checks: "cntr_array:cntrs|cntr_reg:cntr[4].c"
 73. Port Connectivity Checks: "cntr_array:cntrs|cntr_reg:cntr[3].c"
 74. Port Connectivity Checks: "cntr_array:cntrs|cntr_reg:cntr[2].c"
 75. Port Connectivity Checks: "cntr_array:cntrs|cntr_reg:cntr[1].c"
 76. Port Connectivity Checks: "message:msg|uart:uart|uart_rx:rx2"
 77. Port Connectivity Checks: "message:msg|uart:uart|uart_rx:rx1"
 78. Port Connectivity Checks: "message:msg|uart:uart|fifo8:txfifo"
 79. Port Connectivity Checks: "message:msg|uart:uart|baudgen:bgen"
 80. Port Connectivity Checks: "message:msg|uart:uart|pps:rxpps|pps_rx:cx2"
 81. Port Connectivity Checks: "message:msg|uart:uart|pps:rxpps|pps_rx:cx1"
 82. Port Connectivity Checks: "message:msg|uart:uart|pps:rxpps"
 83. Port Connectivity Checks: "message:msg|uart:uart"
 84. Port Connectivity Checks: "frontend:front|packetfifo:f3"
 85. Port Connectivity Checks: "frontend:front|packetfifo:hkfifo|spififo:fifo"
 86. Port Connectivity Checks: "frontend:front|packetfifo:hkfifo"
 87. Port Connectivity Checks: "frontend:front|spi_slave:arm|spififo:fifo"
 88. Port Connectivity Checks: "frontend:front"
 89. Port Connectivity Checks: "pll96:pll0"
 90. Analysis & Synthesis Messages
 91. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
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Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
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(including device programming or simulation files), and any 
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Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                      ;
+------------------------------------+----------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue May 17 08:57:41 2011        ;
; Quartus II Version                 ; 9.1 Build 304 01/25/2010 SP 1 SJ Web Edition ;
; Revision Name                      ; sirena                                       ;
; Top-level Entity Name              ; sirena                                       ;
; Family                             ; Cyclone III                                  ;
; Total logic elements               ; 2,987                                        ;
;     Total combinational functions  ; 2,675                                        ;
;     Dedicated logic registers      ; 1,887                                        ;
; Total registers                    ; 1887                                         ;
; Total pins                         ; 66                                           ;
; Total virtual pins                 ; 0                                            ;
; Total memory bits                  ; 172,032                                      ;
; Embedded Multiplier 9-bit elements ; 0                                            ;
; Total PLLs                         ; 1                                            ;
+------------------------------------+----------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP3C25E144C8       ;                    ;
; Top-level entity name                                                      ; sirena             ; sirena             ;
; Family name                                                                ; Cyclone III        ; Stratix II         ;
; Verilog Show LMF Mapping Messages                                          ; Off                ;                    ;
; Remove Duplicate Registers                                                 ; Off                ; On                 ;
; Optimization Technique                                                     ; Speed              ; Balanced           ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Show Parameter Settings Tables in Synthesis Report                         ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
+----------------------------------------------------------------------------+--------------------+--------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                          ;
+----------------------------------------------------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------------------+
; File Name with User-Entered Path                                           ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                      ;
+----------------------------------------------------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------------------+
; ../../altera/mega/fifo8.v                                                  ; yes             ; User Wizard-Generated File   ; /home/falbala/stephan/solo/pub/eda/altera/mega/fifo8.v                            ;
; uart.v                                                                     ; yes             ; User Verilog HDL File        ; /home/falbala/stephan/solo/pub/eda/sirena/altera/uart.v                           ;
; message.v                                                                  ; yes             ; User Verilog HDL File        ; /home/falbala/stephan/solo/pub/eda/sirena/altera/message.v                        ;
; memory.v                                                                   ; yes             ; User Verilog HDL File        ; /home/falbala/stephan/solo/pub/eda/sirena/altera/memory.v                         ;
; crc.v                                                                      ; yes             ; User Verilog HDL File        ; /home/falbala/stephan/solo/pub/eda/sirena/altera/crc.v                            ;
; core.v                                                                     ; yes             ; User Verilog HDL File        ; /home/falbala/stephan/solo/pub/eda/sirena/altera/core.v                           ;
; ../../altera/packetfifo.v                                                  ; yes             ; User Verilog HDL File        ; /home/falbala/stephan/solo/pub/eda/altera/packetfifo.v                            ;
; ../../altera/frontend.v                                                    ; yes             ; User Verilog HDL File        ; /home/falbala/stephan/solo/pub/eda/altera/frontend.v                              ;
; ../../altera/mega/spififo.v                                                ; yes             ; User Wizard-Generated File   ; /home/falbala/stephan/solo/pub/eda/altera/mega/spififo.v                          ;
; ../../altera/mega/pll96.v                                                  ; yes             ; User Wizard-Generated File   ; /home/falbala/stephan/solo/pub/eda/altera/mega/pll96.v                            ;
; ../../altera/spi_slave.v                                                   ; yes             ; User Verilog HDL File        ; /home/falbala/stephan/solo/pub/eda/altera/spi_slave.v                             ;
; ../../altera/conf_reg.v                                                    ; yes             ; User Verilog HDL File        ; /home/falbala/stephan/solo/pub/eda/altera/conf_reg.v                              ;
; sirena.v                                                                   ; yes             ; User Verilog HDL File        ; /home/falbala/stephan/solo/pub/eda/sirena/altera/sirena.v                         ;
; /usr/local/quartus/altera9.1sp1/quartus/libraries/megafunctions/altpll.tdf ; yes             ; Megafunction                 ; /usr/local/quartus/altera9.1sp1/quartus/libraries/megafunctions/altpll.tdf        ;
; aglobal91.inc                                                              ; yes             ; Megafunction                 ; /usr/local/quartus/altera9.1sp1/quartus/libraries/megafunctions/aglobal91.inc     ;
; stratix_pll.inc                                                            ; yes             ; Megafunction                 ; /usr/local/quartus/altera9.1sp1/quartus/libraries/megafunctions/stratix_pll.inc   ;
; stratixii_pll.inc                                                          ; yes             ; Megafunction                 ; /usr/local/quartus/altera9.1sp1/quartus/libraries/megafunctions/stratixii_pll.inc ;
; cycloneii_pll.inc                                                          ; yes             ; Megafunction                 ; /usr/local/quartus/altera9.1sp1/quartus/libraries/megafunctions/cycloneii_pll.inc ;
; db/altpll_ap03.tdf                                                         ; yes             ; Auto-Generated Megafunction  ; /home/falbala/stephan/solo/pub/eda/sirena/altera/db/altpll_ap03.tdf               ;
; scfifo.tdf                                                                 ; yes             ; Megafunction                 ; /usr/local/quartus/altera9.1sp1/quartus/libraries/megafunctions/scfifo.tdf        ;
; db/scfifo_t0c1.tdf                                                         ; yes             ; Auto-Generated Megafunction  ; /home/falbala/stephan/solo/pub/eda/sirena/altera/db/scfifo_t0c1.tdf               ;
; db/a_dpfifo_0g81.tdf                                                       ; yes             ; Auto-Generated Megafunction  ; /home/falbala/stephan/solo/pub/eda/sirena/altera/db/a_dpfifo_0g81.tdf             ;
; db/altsyncram_l2g1.tdf                                                     ; yes             ; Auto-Generated Megafunction  ; /home/falbala/stephan/solo/pub/eda/sirena/altera/db/altsyncram_l2g1.tdf           ;
; db/cmpr_ms8.tdf                                                            ; yes             ; Auto-Generated Megafunction  ; /home/falbala/stephan/solo/pub/eda/sirena/altera/db/cmpr_ms8.tdf                  ;
; db/cntr_1ab.tdf                                                            ; yes             ; Auto-Generated Megafunction  ; /home/falbala/stephan/solo/pub/eda/sirena/altera/db/cntr_1ab.tdf                  ;
; db/cntr_ea7.tdf                                                            ; yes             ; Auto-Generated Megafunction  ; /home/falbala/stephan/solo/pub/eda/sirena/altera/db/cntr_ea7.tdf                  ;
; db/cntr_2ab.tdf                                                            ; yes             ; Auto-Generated Megafunction  ; /home/falbala/stephan/solo/pub/eda/sirena/altera/db/cntr_2ab.tdf                  ;
; db/scfifo_ns81.tdf                                                         ; yes             ; Auto-Generated Megafunction  ; /home/falbala/stephan/solo/pub/eda/sirena/altera/db/scfifo_ns81.tdf               ;
; db/a_dpfifo_6k81.tdf                                                       ; yes             ; Auto-Generated Megafunction  ; /home/falbala/stephan/solo/pub/eda/sirena/altera/db/a_dpfifo_6k81.tdf             ;
; db/altsyncram_9vf1.tdf                                                     ; yes             ; Auto-Generated Megafunction  ; /home/falbala/stephan/solo/pub/eda/sirena/altera/db/altsyncram_9vf1.tdf           ;
; db/cmpr_ls8.tdf                                                            ; yes             ; Auto-Generated Megafunction  ; /home/falbala/stephan/solo/pub/eda/sirena/altera/db/cmpr_ls8.tdf                  ;
; db/cntr_p8b.tdf                                                            ; yes             ; Auto-Generated Megafunction  ; /home/falbala/stephan/solo/pub/eda/sirena/altera/db/cntr_p8b.tdf                  ;
; db/cntr_da7.tdf                                                            ; yes             ; Auto-Generated Megafunction  ; /home/falbala/stephan/solo/pub/eda/sirena/altera/db/cntr_da7.tdf                  ;
+----------------------------------------------------------------------------+-----------------+------------------------------+-----------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                                        ;
+---------------------------------------------+----------------------------------------------------------------------+
; Resource                                    ; Usage                                                                ;
+---------------------------------------------+----------------------------------------------------------------------+
; Estimated Total logic elements              ; 2,987                                                                ;
;                                             ;                                                                      ;
; Total combinational functions               ; 2675                                                                 ;
; Logic element usage by number of LUT inputs ;                                                                      ;
;     -- 4 input functions                    ; 1228                                                                 ;
;     -- 3 input functions                    ; 662                                                                  ;
;     -- <=2 input functions                  ; 785                                                                  ;
;                                             ;                                                                      ;
; Logic elements by mode                      ;                                                                      ;
;     -- normal mode                          ; 2179                                                                 ;
;     -- arithmetic mode                      ; 496                                                                  ;
;                                             ;                                                                      ;
; Total registers                             ; 1887                                                                 ;
;     -- Dedicated logic registers            ; 1887                                                                 ;
;     -- I/O registers                        ; 0                                                                    ;
;                                             ;                                                                      ;
; I/O pins                                    ; 66                                                                   ;
; Total memory bits                           ; 172032                                                               ;
; Total PLLs                                  ; 1                                                                    ;
; Maximum fan-out node                        ; pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|clk[0] ;
; Maximum fan-out                             ; 1935                                                                 ;
; Total fan-out                               ; 15969                                                                ;
; Average fan-out                             ; 3.32                                                                 ;
+---------------------------------------------+----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                               ;
+------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                     ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                   ; Library Name ;
+------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |sirena                                        ; 2675 (217)        ; 1887 (134)   ; 172032      ; 0            ; 0       ; 0         ; 66   ; 0            ; |sirena                                                                                                                                               ; work         ;
;    |cntr_array:cntrs|                          ; 765 (153)         ; 419 (23)     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|cntr_array:cntrs                                                                                                                              ;              ;
;       |cntr_reg:cntr[1].c|                     ; 102 (102)         ; 66 (65)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|cntr_array:cntrs|cntr_reg:cntr[1].c                                                                                                           ; work         ;
;          |stat_reg:rback|                      ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|cntr_array:cntrs|cntr_reg:cntr[1].c|stat_reg:rback                                                                                            ;              ;
;       |cntr_reg:cntr[2].c|                     ; 102 (102)         ; 66 (65)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|cntr_array:cntrs|cntr_reg:cntr[2].c                                                                                                           ; work         ;
;          |stat_reg:rback|                      ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|cntr_array:cntrs|cntr_reg:cntr[2].c|stat_reg:rback                                                                                            ;              ;
;       |cntr_reg:cntr[3].c|                     ; 102 (102)         ; 66 (65)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|cntr_array:cntrs|cntr_reg:cntr[3].c                                                                                                           ;              ;
;          |stat_reg:rback|                      ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|cntr_array:cntrs|cntr_reg:cntr[3].c|stat_reg:rback                                                                                            ; work         ;
;       |cntr_reg:cntr[4].c|                     ; 102 (102)         ; 66 (65)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|cntr_array:cntrs|cntr_reg:cntr[4].c                                                                                                           ; work         ;
;          |stat_reg:rback|                      ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|cntr_array:cntrs|cntr_reg:cntr[4].c|stat_reg:rback                                                                                            ;              ;
;       |cntr_reg:cntr[5].c|                     ; 102 (102)         ; 66 (65)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|cntr_array:cntrs|cntr_reg:cntr[5].c                                                                                                           ;              ;
;          |stat_reg:rback|                      ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|cntr_array:cntrs|cntr_reg:cntr[5].c|stat_reg:rback                                                                                            ; work         ;
;       |cntr_reg:cntr[6].c|                     ; 102 (102)         ; 66 (65)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|cntr_array:cntrs|cntr_reg:cntr[6].c                                                                                                           ; work         ;
;          |stat_reg:rback|                      ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|cntr_array:cntrs|cntr_reg:cntr[6].c|stat_reg:rback                                                                                            ;              ;
;    |conf_reg:apid_reg|                         ; 15 (1)            ; 18 (17)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|conf_reg:apid_reg                                                                                                                             ;              ;
;       |stat_reg:rback|                         ; 14 (0)            ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|conf_reg:apid_reg|stat_reg:rback                                                                                                              ; work         ;
;          |readback_buffer:b|                   ; 14 (14)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|conf_reg:apid_reg|stat_reg:rback|readback_buffer:b                                                                                            ;              ;
;    |frontend:front|                            ; 1012 (179)        ; 753 (75)     ; 163840      ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front                                                                                                                                ;              ;
;       |cntl_reg:master_conf|                   ; 42 (42)           ; 18 (17)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|cntl_reg:master_conf                                                                                                           ;              ;
;          |stat_reg:rback|                      ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|cntl_reg:master_conf|stat_reg:rback                                                                                            ;              ;
;       |cntr_reg:master_clock|                  ; 102 (102)         ; 66 (65)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|cntr_reg:master_clock                                                                                                          ;              ;
;          |stat_reg:rback|                      ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|cntr_reg:master_clock|stat_reg:rback                                                                                           ;              ;
;       |conf_reg:hkhdrvreg|                     ; 3 (1)             ; 18 (17)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|conf_reg:hkhdrvreg                                                                                                             ;              ;
;          |stat_reg:rback|                      ; 2 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|conf_reg:hkhdrvreg|stat_reg:rback                                                                                              ;              ;
;             |readback_buffer:b|                ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|conf_reg:hkhdrvreg|stat_reg:rback|readback_buffer:b                                                                            ;              ;
;       |conf_reg:hkmaskreg|                     ; 1 (1)             ; 18 (17)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|conf_reg:hkmaskreg                                                                                                             ;              ;
;          |stat_reg:rback|                      ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|conf_reg:hkmaskreg|stat_reg:rback                                                                                              ;              ;
;       |conf_reg:hksizereg|                     ; 1 (1)             ; 18 (17)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|conf_reg:hksizereg                                                                                                             ;              ;
;          |stat_reg:rback|                      ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|conf_reg:hksizereg|stat_reg:rback                                                                                              ;              ;
;       |conf_reg:spide_reg|                     ; 1 (1)             ; 18 (17)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|conf_reg:spide_reg                                                                                                             ;              ;
;          |stat_reg:rback|                      ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|conf_reg:spide_reg|stat_reg:rback                                                                                              ;              ;
;       |error_reg:master_errc|                  ; 20 (20)           ; 17 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|error_reg:master_errc                                                                                                          ;              ;
;          |stat_reg:rback|                      ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|error_reg:master_errc|stat_reg:rback                                                                                           ;              ;
;       |packetfifo:f1|                          ; 135 (57)          ; 83 (35)      ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f1                                                                                                                  ;              ;
;          |spififo:fifo|                        ; 78 (0)            ; 48 (0)       ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f1|spififo:fifo                                                                                                     ;              ;
;             |scfifo:scfifo_component|          ; 78 (0)            ; 48 (0)       ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component                                                                             ;              ;
;                |scfifo_t0c1:auto_generated|    ; 78 (0)            ; 48 (0)       ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated                                                  ;              ;
;                   |a_dpfifo_0g81:dpfifo|       ; 78 (45)           ; 48 (16)      ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo                             ;              ;
;                      |altsyncram_l2g1:FIFOram| ; 0 (0)             ; 0 (0)        ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram     ;              ;
;                      |cntr_1ab:rd_ptr_msb|     ; 11 (11)           ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_1ab:rd_ptr_msb         ;              ;
;                      |cntr_2ab:wr_ptr|         ; 11 (11)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_2ab:wr_ptr             ;              ;
;                      |cntr_ea7:usedw_counter|  ; 11 (11)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_ea7:usedw_counter      ;              ;
;       |packetfifo:f2|                          ; 117 (45)          ; 82 (34)      ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f2                                                                                                                  ;              ;
;          |spififo:fifo|                        ; 72 (0)            ; 48 (0)       ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f2|spififo:fifo                                                                                                     ;              ;
;             |scfifo:scfifo_component|          ; 72 (0)            ; 48 (0)       ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component                                                                             ;              ;
;                |scfifo_t0c1:auto_generated|    ; 72 (0)            ; 48 (0)       ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated                                                  ;              ;
;                   |a_dpfifo_0g81:dpfifo|       ; 72 (37)           ; 48 (16)      ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo                             ;              ;
;                      |altsyncram_l2g1:FIFOram| ; 0 (0)             ; 0 (0)        ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram     ;              ;
;                      |cntr_1ab:rd_ptr_msb|     ; 11 (11)           ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_1ab:rd_ptr_msb         ;              ;
;                      |cntr_2ab:wr_ptr|         ; 12 (12)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_2ab:wr_ptr             ;              ;
;                      |cntr_ea7:usedw_counter|  ; 12 (12)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_ea7:usedw_counter      ;              ;
;       |packetfifo:f3|                          ; 93 (40)           ; 69 (33)      ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f3                                                                                                                  ;              ;
;          |spififo:fifo|                        ; 53 (0)            ; 36 (0)       ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f3|spififo:fifo                                                                                                     ;              ;
;             |scfifo:scfifo_component|          ; 53 (0)            ; 36 (0)       ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component                                                                             ;              ;
;                |scfifo_t0c1:auto_generated|    ; 53 (0)            ; 36 (0)       ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated                                                  ;              ;
;                   |a_dpfifo_0g81:dpfifo|       ; 53 (30)           ; 36 (15)      ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo                             ;              ;
;                      |altsyncram_l2g1:FIFOram| ; 0 (0)             ; 0 (0)        ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram     ;              ;
;                      |cntr_1ab:rd_ptr_msb|     ; 11 (11)           ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_1ab:rd_ptr_msb         ;              ;
;                      |cntr_ea7:usedw_counter|  ; 12 (12)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_ea7:usedw_counter      ;              ;
;       |packetfifo:hkfifo|                      ; 157 (82)          ; 82 (34)      ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:hkfifo                                                                                                              ;              ;
;          |spififo:fifo|                        ; 75 (0)            ; 48 (0)       ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:hkfifo|spififo:fifo                                                                                                 ;              ;
;             |scfifo:scfifo_component|          ; 75 (0)            ; 48 (0)       ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component                                                                         ;              ;
;                |scfifo_t0c1:auto_generated|    ; 75 (0)            ; 48 (0)       ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated                                              ;              ;
;                   |a_dpfifo_0g81:dpfifo|       ; 75 (40)           ; 48 (16)      ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo                         ;              ;
;                      |altsyncram_l2g1:FIFOram| ; 0 (0)             ; 0 (0)        ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram ;              ;
;                      |cntr_1ab:rd_ptr_msb|     ; 11 (11)           ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_1ab:rd_ptr_msb     ;              ;
;                      |cntr_2ab:wr_ptr|         ; 12 (12)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_2ab:wr_ptr         ;              ;
;                      |cntr_ea7:usedw_counter|  ; 12 (12)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_ea7:usedw_counter  ;              ;
;       |reset_reg:master_rsts|                  ; 9 (9)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|reset_reg:master_rsts                                                                                                          ;              ;
;       |spi_slave:arm|                          ; 152 (53)          ; 179 (118)    ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|spi_slave:arm                                                                                                                  ;              ;
;          |spi_timeout:tout|                    ; 19 (19)           ; 12 (12)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|spi_slave:arm|spi_timeout:tout                                                                                                 ;              ;
;          |spififo:fifo|                        ; 80 (0)            ; 49 (0)       ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|spi_slave:arm|spififo:fifo                                                                                                     ;              ;
;             |scfifo:scfifo_component|          ; 80 (0)            ; 49 (0)       ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component                                                                             ;              ;
;                |scfifo_t0c1:auto_generated|    ; 80 (7)            ; 49 (1)       ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated                                                  ;              ;
;                   |a_dpfifo_0g81:dpfifo|       ; 73 (40)           ; 48 (16)      ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo                             ;              ;
;                      |altsyncram_l2g1:FIFOram| ; 0 (0)             ; 0 (0)        ; 32768       ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram     ;              ;
;                      |cntr_1ab:rd_ptr_msb|     ; 11 (11)           ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_1ab:rd_ptr_msb         ;              ;
;                      |cntr_2ab:wr_ptr|         ; 11 (11)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_2ab:wr_ptr             ;              ;
;                      |cntr_ea7:usedw_counter|  ; 11 (11)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_ea7:usedw_counter      ;              ;
;       |stat_reg:master_stat|                   ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|frontend:front|stat_reg:master_stat                                                                                                           ;              ;
;    |message:msg|                               ; 599 (268)         ; 485 (205)    ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|message:msg                                                                                                                                   ;              ;
;       |crc_byte:crc_rx|                        ; 31 (14)           ; 28 (12)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|message:msg|crc_byte:crc_rx                                                                                                                   ;              ;
;          |crc:crc|                             ; 17 (17)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|message:msg|crc_byte:crc_rx|crc:crc                                                                                                           ;              ;
;       |crc_byte:crc_tx|                        ; 31 (15)           ; 28 (12)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|message:msg|crc_byte:crc_tx                                                                                                                   ;              ;
;          |crc:crc|                             ; 16 (16)           ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|message:msg|crc_byte:crc_tx|crc:crc                                                                                                           ; work         ;
;       |uart:uart|                              ; 269 (19)          ; 224 (13)     ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|message:msg|uart:uart                                                                                                                         ;              ;
;          |baudgen:bgen|                        ; 30 (30)           ; 23 (23)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|message:msg|uart:uart|baudgen:bgen                                                                                                            ;              ;
;          |fifo8:txfifo|                        ; 67 (0)            ; 44 (0)       ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|message:msg|uart:uart|fifo8:txfifo                                                                                                            ;              ;
;             |scfifo:scfifo_component|          ; 67 (0)            ; 44 (0)       ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component                                                                                    ; work         ;
;                |scfifo_ns81:auto_generated|    ; 67 (0)            ; 44 (0)       ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated                                                         ;              ;
;                   |a_dpfifo_6k81:dpfifo|       ; 67 (37)           ; 44 (15)      ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo                                    ; work         ;
;                      |altsyncram_9vf1:FIFOram| ; 0 (0)             ; 0 (0)        ; 8192        ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram            ;              ;
;                      |cntr_1ab:wr_ptr|         ; 10 (10)           ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|cntr_1ab:wr_ptr                    ; work         ;
;                      |cntr_da7:usedw_counter|  ; 10 (10)           ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|cntr_da7:usedw_counter             ;              ;
;                      |cntr_p8b:rd_ptr_msb|     ; 10 (10)           ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|cntr_p8b:rd_ptr_msb                ; work         ;
;          |uart_rx:rx1|                         ; 66 (66)           ; 61 (61)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|message:msg|uart:uart|uart_rx:rx1                                                                                                             ;              ;
;          |uart_rx:rx2|                         ; 67 (67)           ; 61 (61)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|message:msg|uart:uart|uart_rx:rx2                                                                                                             ; work         ;
;          |uart_tx:tx|                          ; 20 (20)           ; 22 (22)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|message:msg|uart:uart|uart_tx:tx                                                                                                              ; work         ;
;    |pll96:pll0|                                ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|pll96:pll0                                                                                                                                    ;              ;
;       |altpll:altpll_component|                ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|pll96:pll0|altpll:altpll_component                                                                                                            ;              ;
;          |altpll_ap03:auto_generated|          ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated                                                                                 ;              ;
;    |simcore:core|                              ; 67 (0)            ; 76 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|simcore:core                                                                                                                                  ; work         ;
;       |msg_echo:echo|                          ; 67 (67)           ; 76 (76)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|simcore:core|msg_echo:echo                                                                                                                    ; work         ;
;    |stat_reg:len_reg|                          ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|stat_reg:len_reg                                                                                                                              ; work         ;
;    |stat_reg:stat_reg|                         ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |sirena|stat_reg:stat_reg                                                                                                                             ; work         ;
+------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                              ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
; Name                                                                                                                                                     ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF  ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+
; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ALTSYNCRAM     ; M9K  ; Simple Dual Port ; 2048         ; 16           ; 2048         ; 16           ; 32768 ; None ;
; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ALTSYNCRAM     ; M9K  ; Simple Dual Port ; 2048         ; 16           ; 2048         ; 16           ; 32768 ; None ;
; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ALTSYNCRAM     ; M9K  ; Simple Dual Port ; 2048         ; 16           ; 2048         ; 16           ; 32768 ; None ;
; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ALTSYNCRAM ; M9K  ; Simple Dual Port ; 2048         ; 16           ; 2048         ; 16           ; 32768 ; None ;
; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ALTSYNCRAM     ; M9K  ; Simple Dual Port ; 2048         ; 16           ; 2048         ; 16           ; 32768 ; None ;
; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram|ALTSYNCRAM            ; M9K  ; Simple Dual Port ; 1024         ; 9            ; 1024         ; 9            ; 9216  ; None ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
; Register name                                                                                                                                            ; Reason for Removal                     ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+
; simcore:core|msg_echo:echo|t_len[0,2,4..15]                                                                                                              ; Stuck at GND due to stuck port data_in ;
; simcore:core|msg_echo:echo|t_apid[0..5,8..9,12]                                                                                                          ; Stuck at GND due to stuck port data_in ;
; memory:mem|phase[0]                                                                                                                                      ; Stuck at GND due to stuck port data_in ;
; memory:mem|sram_a[0]                                                                                                                                     ; Stuck at GND due to stuck port data_in ;
; memory:mem|data[0..7]                                                                                                                                    ; Stuck at GND due to stuck port data_in ;
; memory:mem|sram_a[1..20]                                                                                                                                 ; Stuck at GND due to stuck port data_in ;
; memory:mem|phase[1..5]                                                                                                                                   ; Stuck at GND due to stuck port data_in ;
; t_den[2]                                                                                                                                                 ; Stuck at GND due to stuck port data_in ;
; memory:mem|busy                                                                                                                                          ; Stuck at GND due to stuck port data_in ;
; memory:mem|nce                                                                                                                                           ; Stuck at VCC due to stuck port data_in ;
; memory:mem|sram_oe                                                                                                                                       ; Stuck at VCC due to stuck port data_in ;
; memory:mem|sram_we                                                                                                                                       ; Stuck at VCC due to stuck port data_in ;
; memory:mem|oen                                                                                                                                           ; Stuck at GND due to stuck port data_in ;
; memory:mem|write                                                                                                                                         ; Lost fanout                            ;
; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_2ab:wr_ptr|counter_reg_bit[0..10] ; Stuck at GND due to stuck port data_in ;
; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|full_dff                               ; Stuck at GND due to stuck port data_in ;
; frontend:front|error_reg:master_errc|stat[2..3]                                                                                                          ; Stuck at GND due to stuck port data_in ;
; frontend:front|packetfifo:f3|search                                                                                                                      ; Lost fanout                            ;
; frontend:front|packetfifo:f2|search                                                                                                                      ; Lost fanout                            ;
; Total Number of Removed Registers = 81                                                                                                                   ;                                        ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+


+-----------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                         ;
+---------------------+---------------------------+---------------------------------------------------+
; Register name       ; Reason for Removal        ; Registers Removed due to This Register            ;
+---------------------+---------------------------+---------------------------------------------------+
; memory:mem|phase[0] ; Stuck at GND              ; memory:mem|busy, memory:mem|nce, memory:mem|write ;
;                     ; due to stuck port data_in ;                                                   ;
+---------------------+---------------------------+---------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 1887  ;
; Number of registers using Synchronous Clear  ; 112   ;
; Number of registers using Synchronous Load   ; 285   ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 938   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------+
; 3:1                ; 15 bits   ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; Yes        ; |sirena|frontend:front|spi_slave:arm|miso                                           ;
; 3:1                ; 12 bits   ; 24 LEs        ; 12 LEs               ; 12 LEs                 ; Yes        ; |sirena|message:msg|uart:uart|baudgen:bgen|fracdiv[5]                               ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |sirena|frontend:front|spi_slave:arm|rx_data[4]                                     ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |sirena|frontend:front|spi_slave:arm|frame[1]                                       ;
; 3:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; Yes        ; |sirena|cntr_array:cntrs|cntr_reg:cntr[1].c|count[28]                               ;
; 3:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; Yes        ; |sirena|cntr_array:cntrs|cntr_reg:cntr[2].c|count[1]                                ;
; 3:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; Yes        ; |sirena|cntr_array:cntrs|cntr_reg:cntr[3].c|count[18]                               ;
; 3:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; Yes        ; |sirena|cntr_array:cntrs|cntr_reg:cntr[4].c|count[17]                               ;
; 3:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; Yes        ; |sirena|cntr_array:cntrs|cntr_reg:cntr[5].c|count[15]                               ;
; 3:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; Yes        ; |sirena|cntr_array:cntrs|cntr_reg:cntr[6].c|count[16]                               ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |sirena|frontend:front|ww[26]                                                       ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |sirena|frontend:front|ww[0]                                                        ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |sirena|frontend:front|packetfifo:hkfifo|rd[15]                                     ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |sirena|frontend:front|packetfifo:f1|rd[1]                                          ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |sirena|frontend:front|packetfifo:f2|rd[5]                                          ;
; 3:1                ; 15 bits   ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; Yes        ; |sirena|frontend:front|packetfifo:f3|rd[1]                                          ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |sirena|frontend:front|cntr_reg:master_clock|latch[3]                               ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |sirena|frontend:front|cntr_reg:master_clock|latch[16]                              ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |sirena|frontend:front|spi_slave:arm|addr                                           ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |sirena|message:msg|crc_byte:crc_tx|crc:crc|sr[14]                                  ;
; 3:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; Yes        ; |sirena|frontend:front|cntr_reg:master_clock|count[3]                               ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |sirena|message:msg|crc_byte:crc_rx|crc:crc|sr[3]                                   ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |sirena|cntr_array:cntrs|cntr_reg:cntr[1].c|latch[8]                                ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |sirena|cntr_array:cntrs|cntr_reg:cntr[1].c|latch[28]                               ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |sirena|cntr_array:cntrs|cntr_reg:cntr[2].c|latch[14]                               ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |sirena|cntr_array:cntrs|cntr_reg:cntr[2].c|latch[19]                               ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |sirena|cntr_array:cntrs|cntr_reg:cntr[3].c|latch[2]                                ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |sirena|cntr_array:cntrs|cntr_reg:cntr[3].c|latch[29]                               ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |sirena|cntr_array:cntrs|cntr_reg:cntr[4].c|latch[2]                                ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |sirena|cntr_array:cntrs|cntr_reg:cntr[4].c|latch[24]                               ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |sirena|cntr_array:cntrs|cntr_reg:cntr[5].c|latch[7]                                ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |sirena|cntr_array:cntrs|cntr_reg:cntr[5].c|latch[18]                               ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |sirena|cntr_array:cntrs|cntr_reg:cntr[6].c|latch[11]                               ;
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |sirena|cntr_array:cntrs|cntr_reg:cntr[6].c|latch[19]                               ;
; 3:1                ; 18 bits   ; 36 LEs        ; 18 LEs               ; 18 LEs                 ; Yes        ; |sirena|message:msg|timeout_ctr[13]                                                 ;
; 3:1                ; 48 bits   ; 96 LEs        ; 48 LEs               ; 48 LEs                 ; Yes        ; |sirena|simcore:core|msg_echo:echo|t_data[21]                                       ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |sirena|simcore:core|msg_echo:echo|t_data[53]                                       ;
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |sirena|frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[4]            ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |sirena|push_msg_cnt[0]                                                             ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |sirena|cntr_array:cntrs|ww[2]                                                      ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |sirena|cntr_array:cntrs|ww[6]                                                      ;
; 4:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |sirena|frontend:front|ww[12]                                                       ;
; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |sirena|frontend:front|ww[19]                                                       ;
; 4:1                ; 9 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; Yes        ; |sirena|frontend:front|packetfifo:f2|count[4]                                       ;
; 4:1                ; 9 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; Yes        ; |sirena|frontend:front|packetfifo:f3|count[3]                                       ;
; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |sirena|message:msg|crc_byte:crc_tx|bitcount[2]                                     ;
; 4:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |sirena|message:msg|t_count[11]                                                     ;
; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |sirena|message:msg|crc_byte:crc_rx|bitcount[0]                                     ;
; 4:1                ; 9 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; Yes        ; |sirena|frontend:front|packetfifo:f1|count[1]                                       ;
; 4:1                ; 9 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; Yes        ; |sirena|frontend:front|packetfifo:hkfifo|count[5]                                   ;
; 4:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |sirena|frontend:front|cntl_reg:master_conf|stat[7]                                 ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |sirena|message:msg|uart:uart|uart_tx:tx|bc[1]                                      ;
; 5:1                ; 2 bits    ; 6 LEs         ; 2 LEs                ; 4 LEs                  ; Yes        ; |sirena|cntr_array:cntrs|ww[3]                                                      ;
; 9:1                ; 8 bits    ; 48 LEs        ; 8 LEs                ; 40 LEs                 ; Yes        ; |sirena|message:msg|msg_da[20]                                                      ;
; 5:1                ; 8 bits    ; 24 LEs        ; 16 LEs               ; 8 LEs                  ; Yes        ; |sirena|message:msg|tx_sr[0]                                                        ;
; 5:1                ; 19 bits   ; 57 LEs        ; 38 LEs               ; 19 LEs                 ; Yes        ; |sirena|message:msg|tx_sr[36]                                                       ;
; 5:1                ; 21 bits   ; 63 LEs        ; 42 LEs               ; 21 LEs                 ; Yes        ; |sirena|message:msg|tx_sr[8]                                                        ;
; 5:1                ; 16 bits   ; 48 LEs        ; 32 LEs               ; 16 LEs                 ; Yes        ; |sirena|message:msg|tx_data[5]                                                      ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |sirena|message:msg|uart:uart|uart_rx:rx1|good[1]                                   ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |sirena|message:msg|uart:uart|uart_rx:rx2|good[1]                                   ;
; 10:1               ; 8 bits    ; 48 LEs        ; 8 LEs                ; 40 LEs                 ; Yes        ; |sirena|message:msg|msg_da[14]                                                      ;
; 10:1               ; 8 bits    ; 48 LEs        ; 8 LEs                ; 40 LEs                 ; Yes        ; |sirena|message:msg|msg_da[4]                                                       ;
; 10:1               ; 8 bits    ; 48 LEs        ; 8 LEs                ; 40 LEs                 ; Yes        ; |sirena|message:msg|msg_da[62]                                                      ;
; 10:1               ; 8 bits    ; 48 LEs        ; 8 LEs                ; 40 LEs                 ; Yes        ; |sirena|message:msg|msg_da[53]                                                      ;
; 10:1               ; 8 bits    ; 48 LEs        ; 8 LEs                ; 40 LEs                 ; Yes        ; |sirena|message:msg|msg_da[45]                                                      ;
; 10:1               ; 8 bits    ; 48 LEs        ; 8 LEs                ; 40 LEs                 ; Yes        ; |sirena|message:msg|msg_da[34]                                                      ;
; 10:1               ; 8 bits    ; 48 LEs        ; 8 LEs                ; 40 LEs                 ; Yes        ; |sirena|message:msg|msg_da[25]                                                      ;
; 6:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; Yes        ; |sirena|message:msg|msg_phase[3]                                                    ;
; 6:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; Yes        ; |sirena|message:msg|t_phase[1]                                                      ;
; 7:1                ; 10 bits   ; 40 LEs        ; 10 LEs               ; 30 LEs                 ; Yes        ; |sirena|message:msg|uart:uart|uart_rx:rx1|sr[2]                                     ;
; 7:1                ; 10 bits   ; 40 LEs        ; 10 LEs               ; 30 LEs                 ; Yes        ; |sirena|message:msg|uart:uart|uart_rx:rx2|sr[10]                                    ;
; 7:1                ; 3 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |sirena|message:msg|t_shift[3]                                                      ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |sirena|frontend:front|cntr_reg:master_clock|stat_reg:rback|readback_buffer:b|rd[1] ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |sirena|cntr_array:cntrs|cntr_reg:cntr[1].c|stat_reg:rback|readback_buffer:b|rd[8]  ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |sirena|cntr_array:cntrs|cntr_reg:cntr[2].c|stat_reg:rback|readback_buffer:b|rd[13] ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |sirena|cntr_array:cntrs|cntr_reg:cntr[3].c|stat_reg:rback|readback_buffer:b|rd[9]  ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |sirena|cntr_array:cntrs|cntr_reg:cntr[4].c|stat_reg:rback|readback_buffer:b|rd[3]  ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |sirena|cntr_array:cntrs|cntr_reg:cntr[5].c|stat_reg:rback|readback_buffer:b|rd[11] ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |sirena|cntr_array:cntrs|cntr_reg:cntr[6].c|stat_reg:rback|readback_buffer:b|rd[13] ;
; 8:1                ; 16 bits   ; 80 LEs        ; 64 LEs               ; 16 LEs                 ; No         ; |sirena|fifo1[15]                                                                   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                 ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                  ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                     ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                      ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                 ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                  ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                 ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                  ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                 ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                  ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                          ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                           ;
+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |sirena ;
+----------------+----------------------------------+--------------------+
; Parameter Name ; Value                            ; Type               ;
+----------------+----------------------------------+--------------------+
; W              ; 16                               ; Signed Integer     ;
; ICU_ADDR       ; 00000000000000000000000000100000 ; Unsigned Binary    ;
; ICU_CNTR_ADDR  ; 00000000000000000000000001000000 ; Unsigned Binary    ;
; ICU_APID_ADDR  ; 00000000000000000000000000100000 ; Unsigned Binary    ;
; ICU_LEN_ADDR   ; 00000000000000000000000000100001 ; Unsigned Binary    ;
; ICU_WORD_ADDR  ; 00000000000000000000000000100010 ; Unsigned Binary    ;
; ICU_BYTE_ADDR  ; 00000000000000000000000000100011 ; Unsigned Binary    ;
+----------------+----------------------------------+--------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pll96:pll0|altpll:altpll_component ;
+-------------------------------+-------------------+-----------------------------+
; Parameter Name                ; Value             ; Type                        ;
+-------------------------------+-------------------+-----------------------------+
; OPERATION_MODE                ; NO_COMPENSATION   ; Untyped                     ;
; PLL_TYPE                      ; AUTO              ; Untyped                     ;
; QUALIFY_CONF_DONE             ; OFF               ; Untyped                     ;
; COMPENSATE_CLOCK              ; CLK0              ; Untyped                     ;
; SCAN_CHAIN                    ; LONG              ; Untyped                     ;
; PRIMARY_CLOCK                 ; INCLK0            ; Untyped                     ;
; INCLK0_INPUT_FREQUENCY        ; 83333             ; Signed Integer              ;
; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped                     ;
; GATE_LOCK_SIGNAL              ; NO                ; Untyped                     ;
; GATE_LOCK_COUNTER             ; 0                 ; Untyped                     ;
; LOCK_HIGH                     ; 1                 ; Untyped                     ;
; LOCK_LOW                      ; 1                 ; Untyped                     ;
; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped                     ;
; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped                     ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped                     ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped                     ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped                     ;
; SKIP_VCO                      ; OFF               ; Untyped                     ;
; SWITCH_OVER_COUNTER           ; 0                 ; Untyped                     ;
; SWITCH_OVER_TYPE              ; AUTO              ; Untyped                     ;
; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped                     ;
; BANDWIDTH                     ; 0                 ; Untyped                     ;
; BANDWIDTH_TYPE                ; AUTO              ; Untyped                     ;
; SPREAD_FREQUENCY              ; 0                 ; Untyped                     ;
; DOWN_SPREAD                   ; 0                 ; Untyped                     ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped                     ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF               ; Untyped                     ;
; CLK9_MULTIPLY_BY              ; 0                 ; Untyped                     ;
; CLK8_MULTIPLY_BY              ; 0                 ; Untyped                     ;
; CLK7_MULTIPLY_BY              ; 0                 ; Untyped                     ;
; CLK6_MULTIPLY_BY              ; 0                 ; Untyped                     ;
; CLK5_MULTIPLY_BY              ; 1                 ; Untyped                     ;
; CLK4_MULTIPLY_BY              ; 2                 ; Signed Integer              ;
; CLK3_MULTIPLY_BY              ; 1                 ; Signed Integer              ;
; CLK2_MULTIPLY_BY              ; 2                 ; Signed Integer              ;
; CLK1_MULTIPLY_BY              ; 4                 ; Signed Integer              ;
; CLK0_MULTIPLY_BY              ; 8                 ; Signed Integer              ;
; CLK9_DIVIDE_BY                ; 0                 ; Untyped                     ;
; CLK8_DIVIDE_BY                ; 0                 ; Untyped                     ;
; CLK7_DIVIDE_BY                ; 0                 ; Untyped                     ;
; CLK6_DIVIDE_BY                ; 0                 ; Untyped                     ;
; CLK5_DIVIDE_BY                ; 1                 ; Untyped                     ;
; CLK4_DIVIDE_BY                ; 3                 ; Signed Integer              ;
; CLK3_DIVIDE_BY                ; 1                 ; Signed Integer              ;
; CLK2_DIVIDE_BY                ; 1                 ; Signed Integer              ;
; CLK1_DIVIDE_BY                ; 1                 ; Signed Integer              ;
; CLK0_DIVIDE_BY                ; 1                 ; Signed Integer              ;
; CLK9_PHASE_SHIFT              ; 0                 ; Untyped                     ;
; CLK8_PHASE_SHIFT              ; 0                 ; Untyped                     ;
; CLK7_PHASE_SHIFT              ; 0                 ; Untyped                     ;
; CLK6_PHASE_SHIFT              ; 0                 ; Untyped                     ;
; CLK5_PHASE_SHIFT              ; 0                 ; Untyped                     ;
; CLK4_PHASE_SHIFT              ; 5000              ; Untyped                     ;
; CLK3_PHASE_SHIFT              ; 3000              ; Untyped                     ;
; CLK2_PHASE_SHIFT              ; 2000              ; Untyped                     ;
; CLK1_PHASE_SHIFT              ; 1000              ; Untyped                     ;
; CLK0_PHASE_SHIFT              ; 0                 ; Untyped                     ;
; CLK5_TIME_DELAY               ; 0                 ; Untyped                     ;
; CLK4_TIME_DELAY               ; 0                 ; Untyped                     ;
; CLK3_TIME_DELAY               ; 0                 ; Untyped                     ;
; CLK2_TIME_DELAY               ; 0                 ; Untyped                     ;
; CLK1_TIME_DELAY               ; 0                 ; Untyped                     ;
; CLK0_TIME_DELAY               ; 0                 ; Untyped                     ;
; CLK9_DUTY_CYCLE               ; 50                ; Untyped                     ;
; CLK8_DUTY_CYCLE               ; 50                ; Untyped                     ;
; CLK7_DUTY_CYCLE               ; 50                ; Untyped                     ;
; CLK6_DUTY_CYCLE               ; 50                ; Untyped                     ;
; CLK5_DUTY_CYCLE               ; 50                ; Untyped                     ;
; CLK4_DUTY_CYCLE               ; 50                ; Signed Integer              ;
; CLK3_DUTY_CYCLE               ; 50                ; Signed Integer              ;
; CLK2_DUTY_CYCLE               ; 50                ; Signed Integer              ;
; CLK1_DUTY_CYCLE               ; 50                ; Signed Integer              ;
; CLK0_DUTY_CYCLE               ; 50                ; Signed Integer              ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped                     ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped                     ;
; LOCK_WINDOW_UI                ;  0.05             ; Untyped                     ;
; LOCK_WINDOW_UI_BITS           ; UNUSED            ; Untyped                     ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED            ; Untyped                     ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED            ; Untyped                     ;
; DPA_MULTIPLY_BY               ; 0                 ; Untyped                     ;
; DPA_DIVIDE_BY                 ; 1                 ; Untyped                     ;
; DPA_DIVIDER                   ; 0                 ; Untyped                     ;
; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped                     ;
; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped                     ;
; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped                     ;
; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped                     ;
; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped                     ;
; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped                     ;
; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped                     ;
; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped                     ;
; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped                     ;
; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped                     ;
; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped                     ;
; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped                     ;
; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped                     ;
; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped                     ;
; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped                     ;
; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped                     ;
; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped                     ;
; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped                     ;
; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped                     ;
; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped                     ;
; VCO_MULTIPLY_BY               ; 0                 ; Untyped                     ;
; VCO_DIVIDE_BY                 ; 0                 ; Untyped                     ;
; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped                     ;
; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped                     ;
; VCO_MIN                       ; 0                 ; Untyped                     ;
; VCO_MAX                       ; 0                 ; Untyped                     ;
; VCO_CENTER                    ; 0                 ; Untyped                     ;
; PFD_MIN                       ; 0                 ; Untyped                     ;
; PFD_MAX                       ; 0                 ; Untyped                     ;
; M_INITIAL                     ; 0                 ; Untyped                     ;
; M                             ; 0                 ; Untyped                     ;
; N                             ; 1                 ; Untyped                     ;
; M2                            ; 1                 ; Untyped                     ;
; N2                            ; 1                 ; Untyped                     ;
; SS                            ; 1                 ; Untyped                     ;
; C0_HIGH                       ; 0                 ; Untyped                     ;
; C1_HIGH                       ; 0                 ; Untyped                     ;
; C2_HIGH                       ; 0                 ; Untyped                     ;
; C3_HIGH                       ; 0                 ; Untyped                     ;
; C4_HIGH                       ; 0                 ; Untyped                     ;
; C5_HIGH                       ; 0                 ; Untyped                     ;
; C6_HIGH                       ; 0                 ; Untyped                     ;
; C7_HIGH                       ; 0                 ; Untyped                     ;
; C8_HIGH                       ; 0                 ; Untyped                     ;
; C9_HIGH                       ; 0                 ; Untyped                     ;
; C0_LOW                        ; 0                 ; Untyped                     ;
; C1_LOW                        ; 0                 ; Untyped                     ;
; C2_LOW                        ; 0                 ; Untyped                     ;
; C3_LOW                        ; 0                 ; Untyped                     ;
; C4_LOW                        ; 0                 ; Untyped                     ;
; C5_LOW                        ; 0                 ; Untyped                     ;
; C6_LOW                        ; 0                 ; Untyped                     ;
; C7_LOW                        ; 0                 ; Untyped                     ;
; C8_LOW                        ; 0                 ; Untyped                     ;
; C9_LOW                        ; 0                 ; Untyped                     ;
; C0_INITIAL                    ; 0                 ; Untyped                     ;
; C1_INITIAL                    ; 0                 ; Untyped                     ;
; C2_INITIAL                    ; 0                 ; Untyped                     ;
; C3_INITIAL                    ; 0                 ; Untyped                     ;
; C4_INITIAL                    ; 0                 ; Untyped                     ;
; C5_INITIAL                    ; 0                 ; Untyped                     ;
; C6_INITIAL                    ; 0                 ; Untyped                     ;
; C7_INITIAL                    ; 0                 ; Untyped                     ;
; C8_INITIAL                    ; 0                 ; Untyped                     ;
; C9_INITIAL                    ; 0                 ; Untyped                     ;
; C0_MODE                       ; BYPASS            ; Untyped                     ;
; C1_MODE                       ; BYPASS            ; Untyped                     ;
; C2_MODE                       ; BYPASS            ; Untyped                     ;
; C3_MODE                       ; BYPASS            ; Untyped                     ;
; C4_MODE                       ; BYPASS            ; Untyped                     ;
; C5_MODE                       ; BYPASS            ; Untyped                     ;
; C6_MODE                       ; BYPASS            ; Untyped                     ;
; C7_MODE                       ; BYPASS            ; Untyped                     ;
; C8_MODE                       ; BYPASS            ; Untyped                     ;
; C9_MODE                       ; BYPASS            ; Untyped                     ;
; C0_PH                         ; 0                 ; Untyped                     ;
; C1_PH                         ; 0                 ; Untyped                     ;
; C2_PH                         ; 0                 ; Untyped                     ;
; C3_PH                         ; 0                 ; Untyped                     ;
; C4_PH                         ; 0                 ; Untyped                     ;
; C5_PH                         ; 0                 ; Untyped                     ;
; C6_PH                         ; 0                 ; Untyped                     ;
; C7_PH                         ; 0                 ; Untyped                     ;
; C8_PH                         ; 0                 ; Untyped                     ;
; C9_PH                         ; 0                 ; Untyped                     ;
; L0_HIGH                       ; 1                 ; Untyped                     ;
; L1_HIGH                       ; 1                 ; Untyped                     ;
; G0_HIGH                       ; 1                 ; Untyped                     ;
; G1_HIGH                       ; 1                 ; Untyped                     ;
; G2_HIGH                       ; 1                 ; Untyped                     ;
; G3_HIGH                       ; 1                 ; Untyped                     ;
; E0_HIGH                       ; 1                 ; Untyped                     ;
; E1_HIGH                       ; 1                 ; Untyped                     ;
; E2_HIGH                       ; 1                 ; Untyped                     ;
; E3_HIGH                       ; 1                 ; Untyped                     ;
; L0_LOW                        ; 1                 ; Untyped                     ;
; L1_LOW                        ; 1                 ; Untyped                     ;
; G0_LOW                        ; 1                 ; Untyped                     ;
; G1_LOW                        ; 1                 ; Untyped                     ;
; G2_LOW                        ; 1                 ; Untyped                     ;
; G3_LOW                        ; 1                 ; Untyped                     ;
; E0_LOW                        ; 1                 ; Untyped                     ;
; E1_LOW                        ; 1                 ; Untyped                     ;
; E2_LOW                        ; 1                 ; Untyped                     ;
; E3_LOW                        ; 1                 ; Untyped                     ;
; L0_INITIAL                    ; 1                 ; Untyped                     ;
; L1_INITIAL                    ; 1                 ; Untyped                     ;
; G0_INITIAL                    ; 1                 ; Untyped                     ;
; G1_INITIAL                    ; 1                 ; Untyped                     ;
; G2_INITIAL                    ; 1                 ; Untyped                     ;
; G3_INITIAL                    ; 1                 ; Untyped                     ;
; E0_INITIAL                    ; 1                 ; Untyped                     ;
; E1_INITIAL                    ; 1                 ; Untyped                     ;
; E2_INITIAL                    ; 1                 ; Untyped                     ;
; E3_INITIAL                    ; 1                 ; Untyped                     ;
; L0_MODE                       ; BYPASS            ; Untyped                     ;
; L1_MODE                       ; BYPASS            ; Untyped                     ;
; G0_MODE                       ; BYPASS            ; Untyped                     ;
; G1_MODE                       ; BYPASS            ; Untyped                     ;
; G2_MODE                       ; BYPASS            ; Untyped                     ;
; G3_MODE                       ; BYPASS            ; Untyped                     ;
; E0_MODE                       ; BYPASS            ; Untyped                     ;
; E1_MODE                       ; BYPASS            ; Untyped                     ;
; E2_MODE                       ; BYPASS            ; Untyped                     ;
; E3_MODE                       ; BYPASS            ; Untyped                     ;
; L0_PH                         ; 0                 ; Untyped                     ;
; L1_PH                         ; 0                 ; Untyped                     ;
; G0_PH                         ; 0                 ; Untyped                     ;
; G1_PH                         ; 0                 ; Untyped                     ;
; G2_PH                         ; 0                 ; Untyped                     ;
; G3_PH                         ; 0                 ; Untyped                     ;
; E0_PH                         ; 0                 ; Untyped                     ;
; E1_PH                         ; 0                 ; Untyped                     ;
; E2_PH                         ; 0                 ; Untyped                     ;
; E3_PH                         ; 0                 ; Untyped                     ;
; M_PH                          ; 0                 ; Untyped                     ;
; C1_USE_CASC_IN                ; OFF               ; Untyped                     ;
; C2_USE_CASC_IN                ; OFF               ; Untyped                     ;
; C3_USE_CASC_IN                ; OFF               ; Untyped                     ;
; C4_USE_CASC_IN                ; OFF               ; Untyped                     ;
; C5_USE_CASC_IN                ; OFF               ; Untyped                     ;
; C6_USE_CASC_IN                ; OFF               ; Untyped                     ;
; C7_USE_CASC_IN                ; OFF               ; Untyped                     ;
; C8_USE_CASC_IN                ; OFF               ; Untyped                     ;
; C9_USE_CASC_IN                ; OFF               ; Untyped                     ;
; CLK0_COUNTER                  ; G0                ; Untyped                     ;
; CLK1_COUNTER                  ; G0                ; Untyped                     ;
; CLK2_COUNTER                  ; G0                ; Untyped                     ;
; CLK3_COUNTER                  ; G0                ; Untyped                     ;
; CLK4_COUNTER                  ; G0                ; Untyped                     ;
; CLK5_COUNTER                  ; G0                ; Untyped                     ;
; CLK6_COUNTER                  ; E0                ; Untyped                     ;
; CLK7_COUNTER                  ; E1                ; Untyped                     ;
; CLK8_COUNTER                  ; E2                ; Untyped                     ;
; CLK9_COUNTER                  ; E3                ; Untyped                     ;
; L0_TIME_DELAY                 ; 0                 ; Untyped                     ;
; L1_TIME_DELAY                 ; 0                 ; Untyped                     ;
; G0_TIME_DELAY                 ; 0                 ; Untyped                     ;
; G1_TIME_DELAY                 ; 0                 ; Untyped                     ;
; G2_TIME_DELAY                 ; 0                 ; Untyped                     ;
; G3_TIME_DELAY                 ; 0                 ; Untyped                     ;
; E0_TIME_DELAY                 ; 0                 ; Untyped                     ;
; E1_TIME_DELAY                 ; 0                 ; Untyped                     ;
; E2_TIME_DELAY                 ; 0                 ; Untyped                     ;
; E3_TIME_DELAY                 ; 0                 ; Untyped                     ;
; M_TIME_DELAY                  ; 0                 ; Untyped                     ;
; N_TIME_DELAY                  ; 0                 ; Untyped                     ;
; EXTCLK3_COUNTER               ; E3                ; Untyped                     ;
; EXTCLK2_COUNTER               ; E2                ; Untyped                     ;
; EXTCLK1_COUNTER               ; E1                ; Untyped                     ;
; EXTCLK0_COUNTER               ; E0                ; Untyped                     ;
; ENABLE0_COUNTER               ; L0                ; Untyped                     ;
; ENABLE1_COUNTER               ; L0                ; Untyped                     ;
; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped                     ;
; LOOP_FILTER_R                 ;  1.000000         ; Untyped                     ;
; LOOP_FILTER_C                 ; 5                 ; Untyped                     ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999              ; Untyped                     ;
; LOOP_FILTER_R_BITS            ; 9999              ; Untyped                     ;
; LOOP_FILTER_C_BITS            ; 9999              ; Untyped                     ;
; VCO_POST_SCALE                ; 0                 ; Untyped                     ;
; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped                     ;
; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped                     ;
; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped                     ;
; INTENDED_DEVICE_FAMILY        ; Cyclone III       ; Untyped                     ;
; PORT_CLKENA0                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLKENA1                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLKENA2                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLKENA3                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLKENA4                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLKENA5                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_EXTCLK0                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_EXTCLK1                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_EXTCLK2                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_EXTCLK3                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLKBAD0                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLKBAD1                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLK0                     ; PORT_USED         ; Untyped                     ;
; PORT_CLK1                     ; PORT_USED         ; Untyped                     ;
; PORT_CLK2                     ; PORT_USED         ; Untyped                     ;
; PORT_CLK3                     ; PORT_USED         ; Untyped                     ;
; PORT_CLK4                     ; PORT_USED         ; Untyped                     ;
; PORT_CLK5                     ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLK6                     ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLK7                     ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLK8                     ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLK9                     ; PORT_UNUSED       ; Untyped                     ;
; PORT_SCANDATA                 ; PORT_UNUSED       ; Untyped                     ;
; PORT_SCANDATAOUT              ; PORT_UNUSED       ; Untyped                     ;
; PORT_SCANDONE                 ; PORT_UNUSED       ; Untyped                     ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLKLOSS                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_INCLK1                   ; PORT_UNUSED       ; Untyped                     ;
; PORT_INCLK0                   ; PORT_USED         ; Untyped                     ;
; PORT_FBIN                     ; PORT_UNUSED       ; Untyped                     ;
; PORT_PLLENA                   ; PORT_UNUSED       ; Untyped                     ;
; PORT_CLKSWITCH                ; PORT_UNUSED       ; Untyped                     ;
; PORT_ARESET                   ; PORT_UNUSED       ; Untyped                     ;
; PORT_PFDENA                   ; PORT_UNUSED       ; Untyped                     ;
; PORT_SCANCLK                  ; PORT_UNUSED       ; Untyped                     ;
; PORT_SCANACLR                 ; PORT_UNUSED       ; Untyped                     ;
; PORT_SCANREAD                 ; PORT_UNUSED       ; Untyped                     ;
; PORT_SCANWRITE                ; PORT_UNUSED       ; Untyped                     ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_LOCKED                   ; PORT_USED         ; Untyped                     ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED       ; Untyped                     ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_PHASEDONE                ; PORT_UNUSED       ; Untyped                     ;
; PORT_PHASESTEP                ; PORT_UNUSED       ; Untyped                     ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED       ; Untyped                     ;
; PORT_SCANCLKENA               ; PORT_UNUSED       ; Untyped                     ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED       ; Untyped                     ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY ; Untyped                     ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY ; Untyped                     ;
; M_TEST_SOURCE                 ; 5                 ; Untyped                     ;
; C0_TEST_SOURCE                ; 5                 ; Untyped                     ;
; C1_TEST_SOURCE                ; 5                 ; Untyped                     ;
; C2_TEST_SOURCE                ; 5                 ; Untyped                     ;
; C3_TEST_SOURCE                ; 5                 ; Untyped                     ;
; C4_TEST_SOURCE                ; 5                 ; Untyped                     ;
; C5_TEST_SOURCE                ; 5                 ; Untyped                     ;
; C6_TEST_SOURCE                ; 5                 ; Untyped                     ;
; C7_TEST_SOURCE                ; 5                 ; Untyped                     ;
; C8_TEST_SOURCE                ; 5                 ; Untyped                     ;
; C9_TEST_SOURCE                ; 5                 ; Untyped                     ;
; CBXI_PARAMETER                ; altpll_ap03       ; Untyped                     ;
; VCO_FREQUENCY_CONTROL         ; AUTO              ; Untyped                     ;
; VCO_PHASE_SHIFT_STEP          ; 0                 ; Untyped                     ;
; WIDTH_CLOCK                   ; 5                 ; Signed Integer              ;
; WIDTH_PHASECOUNTERSELECT      ; 4                 ; Untyped                     ;
; USING_FBMIMICBIDIR_PORT       ; OFF               ; Untyped                     ;
; DEVICE_FAMILY                 ; Cyclone III       ; Untyped                     ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED            ; Untyped                     ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF               ; Untyped                     ;
; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                  ;
; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                ;
; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                ;
; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE              ;
+-------------------------------+-------------------+-----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front         ;
+----------------+----------------------------------+-----------------+
; Parameter Name ; Value                            ; Type            ;
+----------------+----------------------------------+-----------------+
; W              ; 16                               ; Signed Integer  ;
; RFIFO_ADDR     ; 0                                ; Signed Integer  ;
; RNOOP_ADDR     ; 1                                ; Signed Integer  ;
; SPIDE_ADDR     ; 2                                ; Signed Integer  ;
; MSTAT_ADDR     ; 5                                ; Signed Integer  ;
; MERRC_ADDR     ; 6                                ; Signed Integer  ;
; MRSTS_ADDR     ; 7                                ; Signed Integer  ;
; MCONF_ADDR     ; 8                                ; Signed Integer  ;
; MCLCK_ADDR     ; 12                               ; Signed Integer  ;
; WHK_ADDR       ; 00000000000000000000000000010000 ; Unsigned Binary ;
; RHKS_ADDR      ; 00000000000000000000000000010000 ; Unsigned Binary ;
; RF1S_ADDR      ; 00000000000000000000000000010001 ; Unsigned Binary ;
; RF2S_ADDR      ; 00000000000000000000000000010010 ; Unsigned Binary ;
; RF3S_ADDR      ; 00000000000000000000000000010011 ; Unsigned Binary ;
; RHK_ADDR       ; 00000000000000000000000000010100 ; Unsigned Binary ;
; RF1_ADDR       ; 00000000000000000000000000010101 ; Unsigned Binary ;
; RF2_ADDR       ; 00000000000000000000000000010110 ; Unsigned Binary ;
; RF3_ADDR       ; 00000000000000000000000000010111 ; Unsigned Binary ;
; HKSZ_ADDR      ; 00000000000000000000000000011000 ; Unsigned Binary ;
; HKMA_ADDR      ; 00000000000000000000000000011001 ; Unsigned Binary ;
; HKHV_ADDR      ; 00000000000000000000000000011010 ; Unsigned Binary ;
+----------------+----------------------------------+-----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|spi_slave:arm ;
+----------------+-------+--------------------------------------------------+
; Parameter Name ; Value ; Type                                             ;
+----------------+-------+--------------------------------------------------+
; W              ; 16    ; Signed Integer                                   ;
; Wb             ; 4     ; Signed Integer                                   ;
+----------------+-------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|spi_slave:arm|spi_timeout:tout ;
+----------------+-------+-------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                              ;
+----------------+-------+-------------------------------------------------------------------+
; TIMEOUT        ; 128   ; Signed Integer                                                    ;
+----------------+-------+-------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                   ;
+-------------------------+-------------+------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                             ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                           ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                           ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                         ;
; lpm_width               ; 16          ; Signed Integer                                                         ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                         ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                         ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                ;
; ADD_RAM_OUTPUT_REGISTER ; ON          ; Untyped                                                                ;
; ALMOST_FULL_VALUE       ; 1536        ; Signed Integer                                                         ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                ;
; USE_EAB                 ; ON          ; Untyped                                                                ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                ;
; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                ;
; OPTIMIZE_FOR_SPEED      ; 9           ; Untyped                                                                ;
; CBXI_PARAMETER          ; scfifo_t0c1 ; Untyped                                                                ;
+-------------------------+-------------+------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|conf_reg:spide_reg ;
+----------------+-------+-------------------------------------------------------+
; Parameter Name ; Value ; Type                                                  ;
+----------------+-------+-------------------------------------------------------+
; NB             ; 16    ; Signed Integer                                        ;
+----------------+-------+-------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|conf_reg:spide_reg|stat_reg:rback|readback_buffer:b ;
+----------------+-------+----------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------------+
; W              ; 16    ; Signed Integer                                                                         ;
+----------------+-------+----------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|cntl_reg:master_conf ;
+----------------+-------+---------------------------------------------------------+
; Parameter Name ; Value ; Type                                                    ;
+----------------+-------+---------------------------------------------------------+
; NB             ; 16    ; Signed Integer                                          ;
+----------------+-------+---------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|cntl_reg:master_conf|stat_reg:rback|readback_buffer:b ;
+----------------+-------+------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                     ;
+----------------+-------+------------------------------------------------------------------------------------------+
; W              ; 16    ; Signed Integer                                                                           ;
+----------------+-------+------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|cntr_reg:master_clock|stat_reg:rback|readback_buffer:b ;
+----------------+-------+-------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                      ;
+----------------+-------+-------------------------------------------------------------------------------------------+
; W              ; 16    ; Signed Integer                                                                            ;
+----------------+-------+-------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|stat_reg:master_stat|readback_buffer:b ;
+----------------+-------+---------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                      ;
+----------------+-------+---------------------------------------------------------------------------+
; W              ; 16    ; Signed Integer                                                            ;
+----------------+-------+---------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|error_reg:master_errc|stat_reg:rback|readback_buffer:b ;
+----------------+-------+-------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                      ;
+----------------+-------+-------------------------------------------------------------------------------------------+
; W              ; 16    ; Signed Integer                                                                            ;
+----------------+-------+-------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|conf_reg:hksizereg ;
+----------------+-------+-------------------------------------------------------+
; Parameter Name ; Value ; Type                                                  ;
+----------------+-------+-------------------------------------------------------+
; NB             ; 16    ; Signed Integer                                        ;
+----------------+-------+-------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|conf_reg:hksizereg|stat_reg:rback|readback_buffer:b ;
+----------------+-------+----------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------------+
; W              ; 16    ; Signed Integer                                                                         ;
+----------------+-------+----------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|conf_reg:hkmaskreg ;
+----------------+-------+-------------------------------------------------------+
; Parameter Name ; Value ; Type                                                  ;
+----------------+-------+-------------------------------------------------------+
; NB             ; 16    ; Signed Integer                                        ;
+----------------+-------+-------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|conf_reg:hkmaskreg|stat_reg:rback|readback_buffer:b ;
+----------------+-------+----------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------------+
; W              ; 16    ; Signed Integer                                                                         ;
+----------------+-------+----------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|conf_reg:hkhdrvreg ;
+----------------+-------+-------------------------------------------------------+
; Parameter Name ; Value ; Type                                                  ;
+----------------+-------+-------------------------------------------------------+
; NB             ; 16    ; Signed Integer                                        ;
+----------------+-------+-------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|conf_reg:hkhdrvreg|stat_reg:rback|readback_buffer:b ;
+----------------+-------+----------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------------+
; W              ; 16    ; Signed Integer                                                                         ;
+----------------+-------+----------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|packetfifo:hkfifo ;
+----------------+-------+------------------------------------------------------+
; Parameter Name ; Value ; Type                                                 ;
+----------------+-------+------------------------------------------------------+
; W              ; 16    ; Signed Integer                                       ;
+----------------+-------+------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component ;
+-------------------------+-------------+----------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                       ;
+-------------------------+-------------+----------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                 ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                               ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                               ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                             ;
; lpm_width               ; 16          ; Signed Integer                                                             ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                             ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                             ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                    ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                    ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                    ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                    ;
; ADD_RAM_OUTPUT_REGISTER ; ON          ; Untyped                                                                    ;
; ALMOST_FULL_VALUE       ; 1536        ; Signed Integer                                                             ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                    ;
; USE_EAB                 ; ON          ; Untyped                                                                    ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                    ;
; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                    ;
; OPTIMIZE_FOR_SPEED      ; 9           ; Untyped                                                                    ;
; CBXI_PARAMETER          ; scfifo_t0c1 ; Untyped                                                                    ;
+-------------------------+-------------+----------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|packetfifo:f1 ;
+----------------+-------+--------------------------------------------------+
; Parameter Name ; Value ; Type                                             ;
+----------------+-------+--------------------------------------------------+
; W              ; 16    ; Signed Integer                                   ;
+----------------+-------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                   ;
+-------------------------+-------------+------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                             ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                           ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                           ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                         ;
; lpm_width               ; 16          ; Signed Integer                                                         ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                         ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                         ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                ;
; ADD_RAM_OUTPUT_REGISTER ; ON          ; Untyped                                                                ;
; ALMOST_FULL_VALUE       ; 1536        ; Signed Integer                                                         ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                ;
; USE_EAB                 ; ON          ; Untyped                                                                ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                ;
; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                ;
; OPTIMIZE_FOR_SPEED      ; 9           ; Untyped                                                                ;
; CBXI_PARAMETER          ; scfifo_t0c1 ; Untyped                                                                ;
+-------------------------+-------------+------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|packetfifo:f2 ;
+----------------+-------+--------------------------------------------------+
; Parameter Name ; Value ; Type                                             ;
+----------------+-------+--------------------------------------------------+
; W              ; 16    ; Signed Integer                                   ;
+----------------+-------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                   ;
+-------------------------+-------------+------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                             ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                           ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                           ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                         ;
; lpm_width               ; 16          ; Signed Integer                                                         ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                         ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                         ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                ;
; ADD_RAM_OUTPUT_REGISTER ; ON          ; Untyped                                                                ;
; ALMOST_FULL_VALUE       ; 1536        ; Signed Integer                                                         ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                ;
; USE_EAB                 ; ON          ; Untyped                                                                ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                ;
; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                ;
; OPTIMIZE_FOR_SPEED      ; 9           ; Untyped                                                                ;
; CBXI_PARAMETER          ; scfifo_t0c1 ; Untyped                                                                ;
+-------------------------+-------------+------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|packetfifo:f3 ;
+----------------+-------+--------------------------------------------------+
; Parameter Name ; Value ; Type                                             ;
+----------------+-------+--------------------------------------------------+
; W              ; 16    ; Signed Integer                                   ;
+----------------+-------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component ;
+-------------------------+-------------+------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                   ;
+-------------------------+-------------+------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                             ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                           ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                           ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                         ;
; lpm_width               ; 16          ; Signed Integer                                                         ;
; LPM_NUMWORDS            ; 2048        ; Signed Integer                                                         ;
; LPM_WIDTHU              ; 11          ; Signed Integer                                                         ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                ;
; UNDERFLOW_CHECKING      ; ON          ; Untyped                                                                ;
; OVERFLOW_CHECKING       ; ON          ; Untyped                                                                ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                ;
; ADD_RAM_OUTPUT_REGISTER ; ON          ; Untyped                                                                ;
; ALMOST_FULL_VALUE       ; 1536        ; Signed Integer                                                         ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                ;
; USE_EAB                 ; ON          ; Untyped                                                                ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                ;
; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                                ;
; OPTIMIZE_FOR_SPEED      ; 9           ; Untyped                                                                ;
; CBXI_PARAMETER          ; scfifo_t0c1 ; Untyped                                                                ;
+-------------------------+-------------+------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: message:msg            ;
+----------------+----------------------------------+-----------------+
; Parameter Name ; Value                            ; Type            ;
+----------------+----------------------------------+-----------------+
; MSYNC          ; 0011110000111101                 ; Unsigned Binary ;
; TSYNC          ; 10111110101110101100101011111110 ; Unsigned Binary ;
; TIMEOUT        ; 48000                            ; Signed Integer  ;
+----------------+----------------------------------+-----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: message:msg|crc_byte:crc_rx ;
+----------------+----------------------------------+----------------------+
; Parameter Name ; Value                            ; Type                 ;
+----------------+----------------------------------+----------------------+
; WIDTH          ; 16                               ; Signed Integer       ;
; POLY           ; 00000000000000000001000000100001 ; Unsigned Binary      ;
; INIT           ; 00000000000000001111111111111111 ; Unsigned Binary      ;
; REFOUT         ; 0                                ; Signed Integer       ;
; REFIN          ; 0                                ; Signed Integer       ;
; XOROUT         ; 00000000000000000000000000000000 ; Unsigned Binary      ;
; NE             ; 3                                ; Signed Integer       ;
; N              ; 8                                ; Signed Integer       ;
+----------------+----------------------------------+----------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: message:msg|crc_byte:crc_rx|crc:crc ;
+----------------+----------------------------------+------------------------------+
; Parameter Name ; Value                            ; Type                         ;
+----------------+----------------------------------+------------------------------+
; WIDTH          ; 16                               ; Signed Integer               ;
; POLY           ; 00000000000000000001000000100001 ; Unsigned Binary              ;
; INIT           ; 00000000000000001111111111111111 ; Unsigned Binary              ;
; REFOUT         ; 0                                ; Signed Integer               ;
; REFIN          ; 0                                ; Signed Integer               ;
; XOROUT         ; 00000000000000000000000000000000 ; Unsigned Binary              ;
+----------------+----------------------------------+------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: message:msg|crc_byte:crc_tx ;
+----------------+----------------------------------+----------------------+
; Parameter Name ; Value                            ; Type                 ;
+----------------+----------------------------------+----------------------+
; WIDTH          ; 16                               ; Signed Integer       ;
; POLY           ; 00000000000000000001000000100001 ; Unsigned Binary      ;
; INIT           ; 00000000000000001111111111111111 ; Unsigned Binary      ;
; REFOUT         ; 0                                ; Signed Integer       ;
; REFIN          ; 0                                ; Signed Integer       ;
; XOROUT         ; 00000000000000000000000000000000 ; Unsigned Binary      ;
; NE             ; 3                                ; Signed Integer       ;
; N              ; 8                                ; Signed Integer       ;
+----------------+----------------------------------+----------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: message:msg|crc_byte:crc_tx|crc:crc ;
+----------------+----------------------------------+------------------------------+
; Parameter Name ; Value                            ; Type                         ;
+----------------+----------------------------------+------------------------------+
; WIDTH          ; 16                               ; Signed Integer               ;
; POLY           ; 00000000000000000001000000100001 ; Unsigned Binary              ;
; INIT           ; 00000000000000001111111111111111 ; Unsigned Binary              ;
; REFOUT         ; 0                                ; Signed Integer               ;
; REFIN          ; 0                                ; Signed Integer               ;
; XOROUT         ; 00000000000000000000000000000000 ; Unsigned Binary              ;
+----------------+----------------------------------+------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: message:msg|uart:uart ;
+----------------+----------+----------------------------------------+
; Parameter Name ; Value    ; Type                                   ;
+----------------+----------+----------------------------------------+
; MCLK           ; 48000000 ; Signed Integer                         ;
; BAUD           ; 115200   ; Signed Integer                         ;
; DIV            ; 26       ; Signed Integer                         ;
; BAUDMODULO     ; 120      ; Signed Integer                         ;
; FRAC           ; 5        ; Signed Integer                         ;
; PPSRATE        ; 115200   ; Signed Integer                         ;
; PPSRCUT        ; 13       ; Signed Integer                         ;
+----------------+----------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: message:msg|uart:uart|pps:rxpps|pps_rx:cx1 ;
+----------------+-------+----------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                           ;
+----------------+-------+----------------------------------------------------------------+
; LENGTHCUT      ; 20    ; Signed Integer                                                 ;
+----------------+-------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: message:msg|uart:uart|pps:rxpps|pps_rx:cx2 ;
+----------------+-------+----------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                           ;
+----------------+-------+----------------------------------------------------------------+
; LENGTHCUT      ; 20    ; Signed Integer                                                 ;
+----------------+-------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component ;
+-------------------------+-------------+-----------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                            ;
+-------------------------+-------------+-----------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                      ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                    ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                    ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                  ;
; lpm_width               ; 9           ; Signed Integer                                                  ;
; LPM_NUMWORDS            ; 1024        ; Signed Integer                                                  ;
; LPM_WIDTHU              ; 10          ; Signed Integer                                                  ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                         ;
; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                         ;
; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                         ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                         ;
; ADD_RAM_OUTPUT_REGISTER ; ON          ; Untyped                                                         ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                         ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                         ;
; USE_EAB                 ; ON          ; Untyped                                                         ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                         ;
; DEVICE_FAMILY           ; Cyclone III ; Untyped                                                         ;
; OPTIMIZE_FOR_SPEED      ; 9           ; Untyped                                                         ;
; CBXI_PARAMETER          ; scfifo_ns81 ; Untyped                                                         ;
+-------------------------+-------------+-----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cntr_array:cntrs ;
+----------------+-------+--------------------------------------+
; Parameter Name ; Value ; Type                                 ;
+----------------+-------+--------------------------------------+
; B              ; 4     ; Signed Integer                       ;
; N              ; 6     ; Signed Integer                       ;
+----------------+-------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cntr_array:cntrs|cntr_reg:cntr[1].c|stat_reg:rback|readback_buffer:b ;
+----------------+-------+------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                     ;
+----------------+-------+------------------------------------------------------------------------------------------+
; W              ; 16    ; Signed Integer                                                                           ;
+----------------+-------+------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cntr_array:cntrs|cntr_reg:cntr[2].c|stat_reg:rback|readback_buffer:b ;
+----------------+-------+------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                     ;
+----------------+-------+------------------------------------------------------------------------------------------+
; W              ; 16    ; Signed Integer                                                                           ;
+----------------+-------+------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cntr_array:cntrs|cntr_reg:cntr[3].c|stat_reg:rback|readback_buffer:b ;
+----------------+-------+------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                     ;
+----------------+-------+------------------------------------------------------------------------------------------+
; W              ; 16    ; Signed Integer                                                                           ;
+----------------+-------+------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cntr_array:cntrs|cntr_reg:cntr[4].c|stat_reg:rback|readback_buffer:b ;
+----------------+-------+------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                     ;
+----------------+-------+------------------------------------------------------------------------------------------+
; W              ; 16    ; Signed Integer                                                                           ;
+----------------+-------+------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cntr_array:cntrs|cntr_reg:cntr[5].c|stat_reg:rback|readback_buffer:b ;
+----------------+-------+------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                     ;
+----------------+-------+------------------------------------------------------------------------------------------+
; W              ; 16    ; Signed Integer                                                                           ;
+----------------+-------+------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cntr_array:cntrs|cntr_reg:cntr[6].c|stat_reg:rback|readback_buffer:b ;
+----------------+-------+------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                     ;
+----------------+-------+------------------------------------------------------------------------------------------+
; W              ; 16    ; Signed Integer                                                                           ;
+----------------+-------+------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: conf_reg:apid_reg ;
+----------------+-------+---------------------------------------+
; Parameter Name ; Value ; Type                                  ;
+----------------+-------+---------------------------------------+
; NB             ; 16    ; Signed Integer                        ;
+----------------+-------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: conf_reg:apid_reg|stat_reg:rback|readback_buffer:b ;
+----------------+-------+------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                   ;
+----------------+-------+------------------------------------------------------------------------+
; W              ; 16    ; Signed Integer                                                         ;
+----------------+-------+------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: stat_reg:len_reg|readback_buffer:b ;
+----------------+-------+--------------------------------------------------------+
; Parameter Name ; Value ; Type                                                   ;
+----------------+-------+--------------------------------------------------------+
; W              ; 16    ; Signed Integer                                         ;
+----------------+-------+--------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: stat_reg:stat_reg|readback_buffer:b ;
+----------------+-------+---------------------------------------------------------+
; Parameter Name ; Value ; Type                                                    ;
+----------------+-------+---------------------------------------------------------+
; W              ; 16    ; Signed Integer                                          ;
+----------------+-------+---------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------+
; Parameter Settings for User Entity Instance: memory:mem ;
+----------------+-------+--------------------------------+
; Parameter Name ; Value ; Type                           ;
+----------------+-------+--------------------------------+
; CYCLE          ; 8     ; Signed Integer                 ;
+----------------+-------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                       ;
+-------------------------------+------------------------------------+
; Name                          ; Value                              ;
+-------------------------------+------------------------------------+
; Number of entity instances    ; 1                                  ;
; Entity Instance               ; pll96:pll0|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NO_COMPENSATION                    ;
;     -- PLL_TYPE               ; AUTO                               ;
;     -- PRIMARY_CLOCK          ; INCLK0                             ;
;     -- INCLK0_INPUT_FREQUENCY ; 83333                              ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                  ;
;     -- VCO_MULTIPLY_BY        ; 0                                  ;
;     -- VCO_DIVIDE_BY          ; 0                                  ;
+-------------------------------+------------------------------------+


+----------------------------------------------------------------------------------------------------+
; scfifo Parameter Settings by Entity Instance                                                       ;
+----------------------------+-----------------------------------------------------------------------+
; Name                       ; Value                                                                 ;
+----------------------------+-----------------------------------------------------------------------+
; Number of entity instances ; 6                                                                     ;
; Entity Instance            ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component     ;
;     -- FIFO Type           ; Single Clock                                                          ;
;     -- lpm_width           ; 16                                                                    ;
;     -- LPM_NUMWORDS        ; 2048                                                                  ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                   ;
;     -- USE_EAB             ; ON                                                                    ;
; Entity Instance            ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component ;
;     -- FIFO Type           ; Single Clock                                                          ;
;     -- lpm_width           ; 16                                                                    ;
;     -- LPM_NUMWORDS        ; 2048                                                                  ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                   ;
;     -- USE_EAB             ; ON                                                                    ;
; Entity Instance            ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component     ;
;     -- FIFO Type           ; Single Clock                                                          ;
;     -- lpm_width           ; 16                                                                    ;
;     -- LPM_NUMWORDS        ; 2048                                                                  ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                   ;
;     -- USE_EAB             ; ON                                                                    ;
; Entity Instance            ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component     ;
;     -- FIFO Type           ; Single Clock                                                          ;
;     -- lpm_width           ; 16                                                                    ;
;     -- LPM_NUMWORDS        ; 2048                                                                  ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                   ;
;     -- USE_EAB             ; ON                                                                    ;
; Entity Instance            ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component     ;
;     -- FIFO Type           ; Single Clock                                                          ;
;     -- lpm_width           ; 16                                                                    ;
;     -- LPM_NUMWORDS        ; 2048                                                                  ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                   ;
;     -- USE_EAB             ; ON                                                                    ;
; Entity Instance            ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component            ;
;     -- FIFO Type           ; Single Clock                                                          ;
;     -- lpm_width           ; 9                                                                     ;
;     -- LPM_NUMWORDS        ; 1024                                                                  ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                   ;
;     -- USE_EAB             ; ON                                                                    ;
+----------------------------+-----------------------------------------------------------------------+


+-----------------------------------------------+
; Port Connectivity Checks: "stat_reg:stat_reg" ;
+-------------+-------+----------+--------------+
; Port        ; Type  ; Severity ; Details      ;
+-------------+-------+----------+--------------+
; stat[15..2] ; Input ; Info     ; Stuck at GND ;
+-------------+-------+----------+--------------+


+-----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "cntr_array:cntrs|cntr_reg:cntr[6].c"                                                 ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; Port  ; Type   ; Severity ; Details                                                                             ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; count ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "cntr_array:cntrs|cntr_reg:cntr[5].c"                                                 ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; Port  ; Type   ; Severity ; Details                                                                             ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; count ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "cntr_array:cntrs|cntr_reg:cntr[4].c"                                                 ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; Port  ; Type   ; Severity ; Details                                                                             ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; count ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "cntr_array:cntrs|cntr_reg:cntr[3].c"                                                 ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; Port  ; Type   ; Severity ; Details                                                                             ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; count ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "cntr_array:cntrs|cntr_reg:cntr[2].c"                                                 ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; Port  ; Type   ; Severity ; Details                                                                             ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; count ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "cntr_array:cntrs|cntr_reg:cntr[1].c"                                                 ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; Port  ; Type   ; Severity ; Details                                                                             ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; count ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------+--------+----------+-------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "message:msg|uart:uart|uart_rx:rx2"                                                  ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type   ; Severity ; Details                                                                             ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; brk  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------+--------+----------+-------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "message:msg|uart:uart|uart_rx:rx1"                                                  ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type   ; Severity ; Details                                                                             ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; brk  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------+--------+----------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "message:msg|uart:uart|fifo8:txfifo"                                                    ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                             ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; data[8] ; Input  ; Info     ; Stuck at GND                                                                        ;
; q[8]    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; usedw   ; Output ; Info     ; Explicitly unconnected                                                              ;
+---------+--------+----------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "message:msg|uart:uart|baudgen:bgen"                                                                                                                                                         ;
+----------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port           ; Type  ; Severity ; Details                                                                                                                                                                            ;
+----------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; bauddiv[4..3]  ; Input ; Info     ; Stuck at VCC                                                                                                                                                                       ;
; bauddiv[7..5]  ; Input ; Info     ; Stuck at GND                                                                                                                                                                       ;
; bauddiv[2..1]  ; Input ; Info     ; Stuck at GND                                                                                                                                                                       ;
; bauddiv[0]     ; Input ; Info     ; Stuck at VCC                                                                                                                                                                       ;
; baudfrac[7..3] ; Input ; Info     ; Stuck at GND                                                                                                                                                                       ;
; baudfrac[2]    ; Input ; Info     ; Stuck at VCC                                                                                                                                                                       ;
; baudfrac[1]    ; Input ; Info     ; Stuck at GND                                                                                                                                                                       ;
; baudfrac[0]    ; Input ; Info     ; Stuck at VCC                                                                                                                                                                       ;
; baudmod        ; Input ; Warning  ; Input port expression (32 bits) is wider than the input port (8 bits) it drives.  The 24 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
; baudmod[6..3]  ; Input ; Info     ; Stuck at VCC                                                                                                                                                                       ;
; baudmod[2..0]  ; Input ; Info     ; Stuck at GND                                                                                                                                                                       ;
; baudmod[7]     ; Input ; Info     ; Stuck at GND                                                                                                                                                                       ;
+----------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "message:msg|uart:uart|pps:rxpps|pps_rx:cx2"                                                  ;
+---------------+--------+----------+-------------------------------------------------------------------------------------+
; Port          ; Type   ; Severity ; Details                                                                             ;
+---------------+--------+----------+-------------------------------------------------------------------------------------+
; length[11..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; freq[11..0]   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+---------------+--------+----------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "message:msg|uart:uart|pps:rxpps|pps_rx:cx1"                                                  ;
+---------------+--------+----------+-------------------------------------------------------------------------------------+
; Port          ; Type   ; Severity ; Details                                                                             ;
+---------------+--------+----------+-------------------------------------------------------------------------------------+
; length[11..0] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; freq[11..0]   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+---------------+--------+----------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "message:msg|uart:uart|pps:rxpps"                                                      ;
+--------+--------+----------+-------------------------------------------------------------------------------------+
; Port   ; Type   ; Severity ; Details                                                                             ;
+--------+--------+----------+-------------------------------------------------------------------------------------+
; length ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; freq   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; good   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+--------+--------+----------+-------------------------------------------------------------------------------------+


+---------------------------------------------------+
; Port Connectivity Checks: "message:msg|uart:uart" ;
+-------+-------+----------+------------------------+
; Port  ; Type  ; Severity ; Details                ;
+-------+-------+----------+------------------------+
; txbrk ; Input ; Info     ; Stuck at GND           ;
+-------+-------+----------+------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "frontend:front|packetfifo:f3"                                                                                                                                                         ;
+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port    ; Type   ; Severity ; Details                                                                                                                                                                            ;
+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; rbi     ; Input  ; Warning  ; Input port expression (32 bits) is wider than the input port (1 bits) it drives.  The 31 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
; rbi[-1] ; Input  ; Info     ; Stuck at GND                                                                                                                                                                       ;
; rro     ; Output ; Info     ; Explicitly unconnected                                                                                                                                                             ;
+---------+--------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------+
; Port Connectivity Checks: "frontend:front|packetfifo:hkfifo|spififo:fifo" ;
+-------------+--------+----------+-----------------------------------------+
; Port        ; Type   ; Severity ; Details                                 ;
+-------------+--------+----------+-----------------------------------------+
; almost_full ; Output ; Info     ; Explicitly unconnected                  ;
+-------------+--------+----------+-----------------------------------------+


+--------------------------------------------------------------+
; Port Connectivity Checks: "frontend:front|packetfifo:hkfifo" ;
+------+--------+----------+-----------------------------------+
; Port ; Type   ; Severity ; Details                           ;
+------+--------+----------+-----------------------------------+
; rbo  ; Output ; Info     ; Explicitly unconnected            ;
+------+--------+----------+-----------------------------------+


+-----------------------------------------------------------------------+
; Port Connectivity Checks: "frontend:front|spi_slave:arm|spififo:fifo" ;
+-------+--------+----------+-------------------------------------------+
; Port  ; Type   ; Severity ; Details                                   ;
+-------+--------+----------+-------------------------------------------+
; usedw ; Output ; Info     ; Explicitly unconnected                    ;
+-------+--------+----------+-------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "frontend:front"                                                                                ;
+-----------------+--------+----------+-------------------------------------------------------------------------------------+
; Port            ; Type   ; Severity ; Details                                                                             ;
+-----------------+--------+----------+-------------------------------------------------------------------------------------+
; resets[14..6]   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; resets[4..2]    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; resets[0]       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; confs[11..3]    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; clock           ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; fifo_full[2..1] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; fifo2[14..9]    ; Input  ; Info     ; Stuck at GND                                                                        ;
; fifo2[15]       ; Input  ; Info     ; Stuck at VCC                                                                        ;
; fsiz1[15..3]    ; Input  ; Info     ; Stuck at GND                                                                        ;
; fsiz1[2]        ; Input  ; Info     ; Stuck at VCC                                                                        ;
; fsiz1[1]        ; Input  ; Info     ; Stuck at GND                                                                        ;
; fsiz1[0]        ; Input  ; Info     ; Stuck at VCC                                                                        ;
; fsiz2           ; Input  ; Info     ; Stuck at GND                                                                        ;
; fhma1           ; Input  ; Info     ; Stuck at VCC                                                                        ;
; fhma2           ; Input  ; Info     ; Stuck at GND                                                                        ;
; fhva1[13..10]   ; Input  ; Info     ; Stuck at VCC                                                                        ;
; fhva1[5..2]     ; Input  ; Info     ; Stuck at VCC                                                                        ;
; fhva1[15..14]   ; Input  ; Info     ; Stuck at GND                                                                        ;
; fhva1[9..6]     ; Input  ; Info     ; Stuck at GND                                                                        ;
; fhva1[1]        ; Input  ; Info     ; Stuck at GND                                                                        ;
; fhva1[0]        ; Input  ; Info     ; Stuck at VCC                                                                        ;
; fhva2           ; Input  ; Info     ; Stuck at GND                                                                        ;
+-----------------+--------+----------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "pll96:pll0"                                                                                              ;
+------+--------+----------+----------------------------------------------------------------------------------------------------------+
; Port ; Type   ; Severity ; Details                                                                                                  ;
+------+--------+----------+----------------------------------------------------------------------------------------------------------+
; c0   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
; c2   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
; c3   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
; c4   ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
+------+--------+----------+----------------------------------------------------------------------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Web Edition
    Info: Copyright (C) 1991-2010 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer to the 
    Info: applicable agreement for further details.
    Info: Processing started: Tue May 17 08:57:25 2011
Info: Command: quartus_map sirena.qpf
Info: Found 1 design units, including 1 entities, in source file /home/falbala/stephan/solo/pub/eda/altera/mega/fifo8.v
    Info: Found entity 1: fifo8
Info: Found 6 design units, including 6 entities, in source file uart.v
    Info: Found entity 1: uart_tx
    Info: Found entity 2: uart_rx
    Info: Found entity 3: pps_rx
    Info: Found entity 4: pps
    Info: Found entity 5: baudgen
    Info: Found entity 6: uart
Info: Found 1 design units, including 1 entities, in source file message.v
    Info: Found entity 1: message
Info: Found 1 design units, including 1 entities, in source file memory.v
    Info: Found entity 1: memory
Info: Found 2 design units, including 2 entities, in source file crc.v
    Info: Found entity 1: crc
    Info: Found entity 2: crc_byte
Info: Found 2 design units, including 2 entities, in source file core.v
    Info: Found entity 1: simcore
    Info: Found entity 2: msg_echo
Info: Found 1 design units, including 1 entities, in source file /home/falbala/stephan/solo/pub/eda/altera/mega/sram1024x32.v
    Info: Found entity 1: sram1024x32
Info: Found 1 design units, including 1 entities, in source file /home/falbala/stephan/solo/pub/eda/altera/packetfifo.v
    Info: Found entity 1: packetfifo
Info: Found 1 design units, including 1 entities, in source file /home/falbala/stephan/solo/pub/eda/altera/frontend.v
    Info: Found entity 1: frontend
Info: Found 1 design units, including 1 entities, in source file /home/falbala/stephan/solo/pub/eda/altera/mega/sram.v
    Info: Found entity 1: sram
Info: Found 1 design units, including 1 entities, in source file /home/falbala/stephan/solo/pub/eda/altera/mega/spififo.v
    Info: Found entity 1: spififo
Info: Found 1 design units, including 1 entities, in source file /home/falbala/stephan/solo/pub/eda/altera/mega/pll96.v
    Info: Found entity 1: pll96
Info: Found 2 design units, including 2 entities, in source file /home/falbala/stephan/solo/pub/eda/altera/spi_slave.v
    Info: Found entity 1: spi_slave
    Info: Found entity 2: spi_timeout
Info: Found 9 design units, including 9 entities, in source file /home/falbala/stephan/solo/pub/eda/altera/conf_reg.v
    Info: Found entity 1: conf_reg
    Info: Found entity 2: cntl_reg
    Info: Found entity 3: cntr_reg
    Info: Found entity 4: stat_reg
    Info: Found entity 5: error_reg
    Info: Found entity 6: reset_reg
    Info: Found entity 7: readback_buffer
    Info: Found entity 8: reg_file
    Info: Found entity 9: cntr_array
Info: Found 1 design units, including 1 entities, in source file sirena.v
    Info: Found entity 1: sirena
Info: Elaborating entity "sirena" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at sirena.v(54): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at sirena.v(184): truncated value with size 32 to match size of target (3)
Warning (10034): Output port "debug" at sirena.v(34) has no driver
Info: Elaborating entity "pll96" for hierarchy "pll96:pll0"
Info: Elaborating entity "altpll" for hierarchy "pll96:pll0|altpll:altpll_component"
Info: Elaborated megafunction instantiation "pll96:pll0|altpll:altpll_component"
Info: Instantiated megafunction "pll96:pll0|altpll:altpll_component" with the following parameter:
    Info: Parameter "bandwidth_type" = "AUTO"
    Info: Parameter "clk0_divide_by" = "1"
    Info: Parameter "clk0_duty_cycle" = "50"
    Info: Parameter "clk0_multiply_by" = "8"
    Info: Parameter "clk0_phase_shift" = "0"
    Info: Parameter "clk1_divide_by" = "1"
    Info: Parameter "clk1_duty_cycle" = "50"
    Info: Parameter "clk1_multiply_by" = "4"
    Info: Parameter "clk1_phase_shift" = "1000"
    Info: Parameter "clk2_divide_by" = "1"
    Info: Parameter "clk2_duty_cycle" = "50"
    Info: Parameter "clk2_multiply_by" = "2"
    Info: Parameter "clk2_phase_shift" = "2000"
    Info: Parameter "clk3_divide_by" = "1"
    Info: Parameter "clk3_duty_cycle" = "50"
    Info: Parameter "clk3_multiply_by" = "1"
    Info: Parameter "clk3_phase_shift" = "3000"
    Info: Parameter "clk4_divide_by" = "3"
    Info: Parameter "clk4_duty_cycle" = "50"
    Info: Parameter "clk4_multiply_by" = "2"
    Info: Parameter "clk4_phase_shift" = "5000"
    Info: Parameter "inclk0_input_frequency" = "83333"
    Info: Parameter "intended_device_family" = "Cyclone III"
    Info: Parameter "lpm_type" = "altpll"
    Info: Parameter "operation_mode" = "NO_COMPENSATION"
    Info: Parameter "pll_type" = "AUTO"
    Info: Parameter "port_activeclock" = "PORT_UNUSED"
    Info: Parameter "port_areset" = "PORT_UNUSED"
    Info: Parameter "port_clkbad0" = "PORT_UNUSED"
    Info: Parameter "port_clkbad1" = "PORT_UNUSED"
    Info: Parameter "port_clkloss" = "PORT_UNUSED"
    Info: Parameter "port_clkswitch" = "PORT_UNUSED"
    Info: Parameter "port_configupdate" = "PORT_UNUSED"
    Info: Parameter "port_fbin" = "PORT_UNUSED"
    Info: Parameter "port_inclk0" = "PORT_USED"
    Info: Parameter "port_inclk1" = "PORT_UNUSED"
    Info: Parameter "port_locked" = "PORT_USED"
    Info: Parameter "port_pfdena" = "PORT_UNUSED"
    Info: Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info: Parameter "port_phasedone" = "PORT_UNUSED"
    Info: Parameter "port_phasestep" = "PORT_UNUSED"
    Info: Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info: Parameter "port_pllena" = "PORT_UNUSED"
    Info: Parameter "port_scanaclr" = "PORT_UNUSED"
    Info: Parameter "port_scanclk" = "PORT_UNUSED"
    Info: Parameter "port_scanclkena" = "PORT_UNUSED"
    Info: Parameter "port_scandata" = "PORT_UNUSED"
    Info: Parameter "port_scandataout" = "PORT_UNUSED"
    Info: Parameter "port_scandone" = "PORT_UNUSED"
    Info: Parameter "port_scanread" = "PORT_UNUSED"
    Info: Parameter "port_scanwrite" = "PORT_UNUSED"
    Info: Parameter "port_clk0" = "PORT_USED"
    Info: Parameter "port_clk1" = "PORT_USED"
    Info: Parameter "port_clk2" = "PORT_USED"
    Info: Parameter "port_clk3" = "PORT_USED"
    Info: Parameter "port_clk4" = "PORT_USED"
    Info: Parameter "port_clk5" = "PORT_UNUSED"
    Info: Parameter "port_clkena0" = "PORT_UNUSED"
    Info: Parameter "port_clkena1" = "PORT_UNUSED"
    Info: Parameter "port_clkena2" = "PORT_UNUSED"
    Info: Parameter "port_clkena3" = "PORT_UNUSED"
    Info: Parameter "port_clkena4" = "PORT_UNUSED"
    Info: Parameter "port_clkena5" = "PORT_UNUSED"
    Info: Parameter "port_extclk0" = "PORT_UNUSED"
    Info: Parameter "port_extclk1" = "PORT_UNUSED"
    Info: Parameter "port_extclk2" = "PORT_UNUSED"
    Info: Parameter "port_extclk3" = "PORT_UNUSED"
    Info: Parameter "self_reset_on_loss_lock" = "OFF"
    Info: Parameter "width_clock" = "5"
Info: Found 1 design units, including 1 entities, in source file db/altpll_ap03.tdf
    Info: Found entity 1: altpll_ap03
Info: Elaborating entity "altpll_ap03" for hierarchy "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated"
Info: Elaborating entity "frontend" for hierarchy "frontend:front"
Info: Elaborating entity "spi_slave" for hierarchy "frontend:front|spi_slave:arm"
Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at spi_slave.v(101): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "spi_timeout" for hierarchy "frontend:front|spi_slave:arm|spi_timeout:tout"
Warning (10230): Verilog HDL assignment warning at spi_slave.v(257): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at spi_slave.v(259): truncated value with size 32 to match size of target (8)
Info: Elaborating entity "spififo" for hierarchy "frontend:front|spi_slave:arm|spififo:fifo"
Info: Elaborating entity "scfifo" for hierarchy "frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component"
Info: Elaborated megafunction instantiation "frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component"
Info: Instantiated megafunction "frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component" with the following parameter:
    Info: Parameter "add_ram_output_register" = "ON"
    Info: Parameter "almost_full_value" = "1536"
    Info: Parameter "intended_device_family" = "Cyclone III"
    Info: Parameter "lpm_hint" = "RAM_BLOCK_TYPE=M9K"
    Info: Parameter "lpm_numwords" = "2048"
    Info: Parameter "lpm_showahead" = "OFF"
    Info: Parameter "lpm_type" = "scfifo"
    Info: Parameter "lpm_width" = "16"
    Info: Parameter "lpm_widthu" = "11"
    Info: Parameter "overflow_checking" = "ON"
    Info: Parameter "underflow_checking" = "ON"
    Info: Parameter "use_eab" = "ON"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_t0c1.tdf
    Info: Found entity 1: scfifo_t0c1
Info: Elaborating entity "scfifo_t0c1" for hierarchy "frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_0g81.tdf
    Info: Found entity 1: a_dpfifo_0g81
Info: Elaborating entity "a_dpfifo_0g81" for hierarchy "frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_l2g1.tdf
    Info: Found entity 1: altsyncram_l2g1
Info: Elaborating entity "altsyncram_l2g1" for hierarchy "frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram"
Info: Found 1 design units, including 1 entities, in source file db/cmpr_ms8.tdf
    Info: Found entity 1: cmpr_ms8
Info: Elaborating entity "cmpr_ms8" for hierarchy "frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cmpr_ms8:almost_full_comparer"
Info: Elaborating entity "cmpr_ms8" for hierarchy "frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cmpr_ms8:two_comparison"
Info: Found 1 design units, including 1 entities, in source file db/cntr_1ab.tdf
    Info: Found entity 1: cntr_1ab
Info: Elaborating entity "cntr_1ab" for hierarchy "frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_1ab:rd_ptr_msb"
Info: Found 1 design units, including 1 entities, in source file db/cntr_ea7.tdf
    Info: Found entity 1: cntr_ea7
Info: Elaborating entity "cntr_ea7" for hierarchy "frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_ea7:usedw_counter"
Info: Found 1 design units, including 1 entities, in source file db/cntr_2ab.tdf
    Info: Found entity 1: cntr_2ab
Info: Elaborating entity "cntr_2ab" for hierarchy "frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_2ab:wr_ptr"
Info: Elaborating entity "conf_reg" for hierarchy "frontend:front|conf_reg:spide_reg"
Info: Elaborating entity "stat_reg" for hierarchy "frontend:front|conf_reg:spide_reg|stat_reg:rback"
Info: Elaborating entity "readback_buffer" for hierarchy "frontend:front|conf_reg:spide_reg|stat_reg:rback|readback_buffer:b"
Info: Elaborating entity "cntl_reg" for hierarchy "frontend:front|cntl_reg:master_conf"
Info: Elaborating entity "cntr_reg" for hierarchy "frontend:front|cntr_reg:master_clock"
Info: Elaborating entity "error_reg" for hierarchy "frontend:front|error_reg:master_errc"
Info: Elaborating entity "reset_reg" for hierarchy "frontend:front|reset_reg:master_rsts"
Info: Elaborating entity "packetfifo" for hierarchy "frontend:front|packetfifo:hkfifo"
Warning (10230): Verilog HDL assignment warning at packetfifo.v(105): truncated value with size 32 to match size of target (9)
Info: Elaborating entity "message" for hierarchy "message:msg"
Warning (10230): Verilog HDL assignment warning at message.v(70): truncated value with size 32 to match size of target (18)
Warning (10230): Verilog HDL assignment warning at message.v(72): truncated value with size 32 to match size of target (18)
Warning (10230): Verilog HDL assignment warning at message.v(144): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at message.v(220): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at message.v(230): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at message.v(235): truncated value with size 32 to match size of target (13)
Info: Elaborating entity "crc_byte" for hierarchy "message:msg|crc_byte:crc_rx"
Warning (10230): Verilog HDL assignment warning at crc.v(65): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "crc" for hierarchy "message:msg|crc_byte:crc_rx|crc:crc"
Warning (10230): Verilog HDL assignment warning at crc.v(18): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at crc.v(22): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at crc.v(27): truncated value with size 32 to match size of target (16)
Info: Elaborating entity "uart" for hierarchy "message:msg|uart:uart"
Warning (10230): Verilog HDL assignment warning at uart.v(413): truncated value with size 32 to match size of target (17)
Warning (10230): Verilog HDL assignment warning at uart.v(416): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at uart.v(417): truncated value with size 32 to match size of target (8)
Info: Elaborating entity "pps" for hierarchy "message:msg|uart:uart|pps:rxpps"
Info: Elaborating entity "pps_rx" for hierarchy "message:msg|uart:uart|pps:rxpps|pps_rx:cx1"
Warning (10230): Verilog HDL assignment warning at uart.v(222): truncated value with size 32 to match size of target (28)
Info: Elaborating entity "baudgen" for hierarchy "message:msg|uart:uart|baudgen:bgen"
Warning (10230): Verilog HDL assignment warning at uart.v(338): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at uart.v(357): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "uart_tx" for hierarchy "message:msg|uart:uart|uart_tx:tx"
Info: Elaborating entity "fifo8" for hierarchy "message:msg|uart:uart|fifo8:txfifo"
Info: Elaborating entity "scfifo" for hierarchy "message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component"
Info: Elaborated megafunction instantiation "message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component"
Info: Instantiated megafunction "message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component" with the following parameter:
    Info: Parameter "add_ram_output_register" = "ON"
    Info: Parameter "intended_device_family" = "Cyclone III"
    Info: Parameter "lpm_hint" = "RAM_BLOCK_TYPE=M9K"
    Info: Parameter "lpm_numwords" = "1024"
    Info: Parameter "lpm_showahead" = "OFF"
    Info: Parameter "lpm_type" = "scfifo"
    Info: Parameter "lpm_width" = "9"
    Info: Parameter "lpm_widthu" = "10"
    Info: Parameter "overflow_checking" = "OFF"
    Info: Parameter "underflow_checking" = "OFF"
    Info: Parameter "use_eab" = "ON"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_ns81.tdf
    Info: Found entity 1: scfifo_ns81
Info: Elaborating entity "scfifo_ns81" for hierarchy "message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_6k81.tdf
    Info: Found entity 1: a_dpfifo_6k81
Info: Elaborating entity "a_dpfifo_6k81" for hierarchy "message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_9vf1.tdf
    Info: Found entity 1: altsyncram_9vf1
Info: Elaborating entity "altsyncram_9vf1" for hierarchy "message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram"
Info: Found 1 design units, including 1 entities, in source file db/cmpr_ls8.tdf
    Info: Found entity 1: cmpr_ls8
Info: Elaborating entity "cmpr_ls8" for hierarchy "message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|cmpr_ls8:almost_full_comparer"
Info: Elaborating entity "cmpr_ls8" for hierarchy "message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|cmpr_ls8:two_comparison"
Info: Found 1 design units, including 1 entities, in source file db/cntr_p8b.tdf
    Info: Found entity 1: cntr_p8b
Info: Elaborating entity "cntr_p8b" for hierarchy "message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|cntr_p8b:rd_ptr_msb"
Info: Found 1 design units, including 1 entities, in source file db/cntr_da7.tdf
    Info: Found entity 1: cntr_da7
Info: Elaborating entity "cntr_da7" for hierarchy "message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|cntr_da7:usedw_counter"
Info: Elaborating entity "uart_rx" for hierarchy "message:msg|uart:uart|uart_rx:rx1"
Warning (10230): Verilog HDL assignment warning at uart.v(90): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "cntr_array" for hierarchy "cntr_array:cntrs"
Warning (10230): Verilog HDL assignment warning at conf_reg.v(255): truncated value with size 32 to match size of target (6)
Info: Elaborating entity "memory" for hierarchy "memory:mem"
Warning (10230): Verilog HDL assignment warning at memory.v(167): truncated value with size 32 to match size of target (8)
Info: Elaborating entity "simcore" for hierarchy "simcore:core"
Warning (10034): Output port "errors" at core.v(13) has no driver
Warning (10034): Output port "stats" at core.v(13) has no driver
Warning (10034): Output port "fifo" at core.v(24) has no driver
Warning (10034): Output port "fhva" at core.v(25) has no driver
Warning (10034): Output port "m_a" at core.v(44) has no driver
Warning (10034): Output port "m_dwr" at core.v(45) has no driver
Info: Elaborating entity "msg_echo" for hierarchy "simcore:core|msg_echo:echo"
Warning: Synthesized away the following node(s):
    Warning: Synthesized away the following RAM node(s):
        Warning (14320): Synthesized away node "message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram|q_b[8]"
Info: Timing-Driven Synthesis is running
Warning: 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Warning: The following bidir pins have no drivers
    Warning: Bidir "FE_port[0]" has no driver
    Warning: Bidir "FE_port[1]" has no driver
    Warning: Bidir "FE_port[2]" has no driver
    Warning: Bidir "FE_port[3]" has no driver
    Warning: Bidir "FE_port[4]" has no driver
    Warning: Bidir "FE_port[5]" has no driver
    Warning: Bidir "FE_port[6]" has no driver
    Warning: Bidir "FE_port[7]" has no driver
    Warning: Bidir "FE_port[8]" has no driver
    Warning: Bidir "FE_port[9]" has no driver
    Warning: Bidir "FE_port[10]" has no driver
    Warning: Bidir "FE_port[11]" has no driver
    Warning: Bidir "FE_port[12]" has no driver
    Warning: Bidir "FE_port[13]" has no driver
    Warning: Bidir "FE_port[14]" has no driver
    Warning: Bidir "FE_port[15]" has no driver
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "sram_a[0]" is stuck at GND
    Warning (13410): Pin "sram_a[1]" is stuck at GND
    Warning (13410): Pin "sram_a[2]" is stuck at GND
    Warning (13410): Pin "sram_a[3]" is stuck at GND
    Warning (13410): Pin "sram_a[4]" is stuck at GND
    Warning (13410): Pin "sram_a[5]" is stuck at GND
    Warning (13410): Pin "sram_a[6]" is stuck at GND
    Warning (13410): Pin "sram_a[7]" is stuck at GND
    Warning (13410): Pin "sram_a[8]" is stuck at GND
    Warning (13410): Pin "sram_a[9]" is stuck at GND
    Warning (13410): Pin "sram_a[10]" is stuck at GND
    Warning (13410): Pin "sram_a[11]" is stuck at GND
    Warning (13410): Pin "sram_a[12]" is stuck at GND
    Warning (13410): Pin "sram_a[13]" is stuck at GND
    Warning (13410): Pin "sram_a[14]" is stuck at GND
    Warning (13410): Pin "sram_a[15]" is stuck at GND
    Warning (13410): Pin "sram_a[16]" is stuck at GND
    Warning (13410): Pin "sram_a[17]" is stuck at GND
    Warning (13410): Pin "sram_a[18]" is stuck at GND
    Warning (13410): Pin "sram_a[19]" is stuck at GND
    Warning (13410): Pin "sram_a[20]" is stuck at GND
    Warning (13410): Pin "sram_ce[2]" is stuck at VCC
    Warning (13410): Pin "sram_ce[1]" is stuck at VCC
    Warning (13410): Pin "sram_oe" is stuck at VCC
    Warning (13410): Pin "sram_we" is stuck at VCC
    Warning (13410): Pin "debug[6]" is stuck at GND
    Warning (13410): Pin "debug[5]" is stuck at GND
    Warning (13410): Pin "debug[4]" is stuck at GND
Info: 3 registers lost all their fanouts during netlist optimizations. The first 3 are displayed below.
    Info: Register "memory:mem|write" lost all its fanouts during netlist optimizations.
    Info: Register "frontend:front|packetfifo:f3|search" lost all its fanouts during netlist optimizations.
    Info: Register "frontend:front|packetfifo:f2|search" lost all its fanouts during netlist optimizations.
Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" has parameters clk0_multiply_by and clk0_divide_by specified but port CLK[0] is not connected
Info: Starting physical synthesis optimizations for speed
Info: Timing-driven compilation is using the TimeQuest Timing Analyzer
Info: Reading SDC File: 'sirena.sdc'
Info: Deriving PLL Clocks
    Info: create_generated_clock -source {pll0|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -phase 17.31 -duty_cycle 50.00 -name {pll0|altpll_component|auto_generated|pll1|clk[1]} {pll0|altpll_component|auto_generated|pll1|clk[1]}
Info: Clock uncertainty calculation is delayed until the next update_timing_netlist call
Info: The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info: Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info: Found 4 clocks
    Info:   Period   Clock Name
    Info: ======== ============
    Info:   83.333       clk_12
    Info:   66.667       clk_T1
    Info:   20.833 pll0|altpll_component|auto_generated|pll1|clk[1]
    Info:   33.333      spi_sck
Info: Starting physical synthesis algorithm register retiming
Info: Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps
Info: Starting physical synthesis algorithm combinational resynthesis using boolean division
Info: Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
Info: Physical synthesis optimizations for speed complete: elapsed CPU time is 00:00:02
Info: Generated suppressed messages file /home/falbala/stephan/solo/pub/eda/sirena/altera/sirena.map.smsg
Warning: PLL "pll96:pll0|altpll:altpll_component|altpll_ap03:auto_generated|pll1" has parameters clk0_multiply_by and clk0_divide_by specified but port CLK[0] is not connected
Warning: Design contains 5 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "clk_T1"
    Warning (15610): No output dependent on input pin "trigger"
    Warning (15610): No output dependent on input pin "Rx[4]"
    Warning (15610): No output dependent on input pin "Rx[1]"
    Warning (15610): No output dependent on input pin "FE_clk"
Info: Implemented 3173 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 32 output pins
    Info: Implemented 24 bidirectional pins
    Info: Implemented 3018 logic cells
    Info: Implemented 88 RAM segments
    Info: Implemented 1 PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 91 warnings
    Info: Peak virtual memory: 220 megabytes
    Info: Processing ended: Tue May 17 08:57:41 2011
    Info: Elapsed time: 00:00:16
    Info: Total CPU time (on all processors): 00:00:16


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in /home/falbala/stephan/solo/pub/eda/sirena/altera/sirena.map.smsg.


