TimeQuest Timing Analyzer report for sirena
Tue May 17 08:58:39 2011
Quartus II Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Slow 1200mV 85C Model Setup Summary
  8. Slow 1200mV 85C Model Hold Summary
  9. Slow 1200mV 85C Model Recovery Summary
 10. Slow 1200mV 85C Model Removal Summary
 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
 12. Slow 1200mV 85C Model Setup: 'pll0|altpll_component|auto_generated|pll1|clk[1]'
 13. Slow 1200mV 85C Model Setup: 'spi_sck'
 14. Slow 1200mV 85C Model Hold: 'pll0|altpll_component|auto_generated|pll1|clk[1]'
 15. Slow 1200mV 85C Model Hold: 'spi_sck'
 16. Slow 1200mV 85C Model Minimum Pulse Width: 'pll0|altpll_component|auto_generated|pll1|clk[1]'
 17. Slow 1200mV 85C Model Minimum Pulse Width: 'spi_sck'
 18. Slow 1200mV 85C Model Minimum Pulse Width: 'clk_12'
 19. Slow 1200mV 85C Model Minimum Pulse Width: 'clk_T1'
 20. Setup Times
 21. Hold Times
 22. Clock to Output Times
 23. Minimum Clock to Output Times
 24. Propagation Delay
 25. Minimum Propagation Delay
 26. Slow 1200mV 85C Model Metastability Report
 27. Slow 1200mV 0C Model Fmax Summary
 28. Slow 1200mV 0C Model Setup Summary
 29. Slow 1200mV 0C Model Hold Summary
 30. Slow 1200mV 0C Model Recovery Summary
 31. Slow 1200mV 0C Model Removal Summary
 32. Slow 1200mV 0C Model Minimum Pulse Width Summary
 33. Slow 1200mV 0C Model Setup: 'pll0|altpll_component|auto_generated|pll1|clk[1]'
 34. Slow 1200mV 0C Model Setup: 'spi_sck'
 35. Slow 1200mV 0C Model Hold: 'pll0|altpll_component|auto_generated|pll1|clk[1]'
 36. Slow 1200mV 0C Model Hold: 'spi_sck'
 37. Slow 1200mV 0C Model Minimum Pulse Width: 'pll0|altpll_component|auto_generated|pll1|clk[1]'
 38. Slow 1200mV 0C Model Minimum Pulse Width: 'spi_sck'
 39. Slow 1200mV 0C Model Minimum Pulse Width: 'clk_12'
 40. Slow 1200mV 0C Model Minimum Pulse Width: 'clk_T1'
 41. Setup Times
 42. Hold Times
 43. Clock to Output Times
 44. Minimum Clock to Output Times
 45. Propagation Delay
 46. Minimum Propagation Delay
 47. Slow 1200mV 0C Model Metastability Report
 48. Fast 1200mV 0C Model Setup Summary
 49. Fast 1200mV 0C Model Hold Summary
 50. Fast 1200mV 0C Model Recovery Summary
 51. Fast 1200mV 0C Model Removal Summary
 52. Fast 1200mV 0C Model Minimum Pulse Width Summary
 53. Fast 1200mV 0C Model Setup: 'pll0|altpll_component|auto_generated|pll1|clk[1]'
 54. Fast 1200mV 0C Model Setup: 'spi_sck'
 55. Fast 1200mV 0C Model Hold: 'pll0|altpll_component|auto_generated|pll1|clk[1]'
 56. Fast 1200mV 0C Model Hold: 'spi_sck'
 57. Fast 1200mV 0C Model Minimum Pulse Width: 'pll0|altpll_component|auto_generated|pll1|clk[1]'
 58. Fast 1200mV 0C Model Minimum Pulse Width: 'spi_sck'
 59. Fast 1200mV 0C Model Minimum Pulse Width: 'clk_12'
 60. Fast 1200mV 0C Model Minimum Pulse Width: 'clk_T1'
 61. Setup Times
 62. Hold Times
 63. Clock to Output Times
 64. Minimum Clock to Output Times
 65. Propagation Delay
 66. Minimum Propagation Delay
 67. Fast 1200mV 0C Model Metastability Report
 68. Multicorner Timing Analysis Summary
 69. Setup Times
 70. Hold Times
 71. Clock to Output Times
 72. Minimum Clock to Output Times
 73. Progagation Delay
 74. Minimum Progagation Delay
 75. Board Trace Model Assignments
 76. Input Transition Times
 77. Slow Corner Signal Integrity Metrics
 78. Fast Corner Signal Integrity Metrics
 79. Setup Transfers
 80. Hold Transfers
 81. Report TCCS
 82. Report RSKM
 83. Unconstrained Paths
 84. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                   ;
+--------------------+----------------------------------------------------------------+
; Quartus II Version ; Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Web Edition ;
; Revision Name      ; sirena                                                         ;
; Device Family      ; Cyclone III                                                    ;
; Device Name        ; EP3C25E144C8                                                   ;
; Timing Models      ; Final                                                          ;
; Delay Model        ; Combined                                                       ;
; Rise/Fall Delays   ; Enabled                                                        ;
+--------------------+----------------------------------------------------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+---------------------------------------------------+
; SDC File List                                     ;
+---------------+--------+--------------------------+
; SDC File Path ; Status ; Read at                  ;
+---------------+--------+--------------------------+
; sirena.sdc    ; OK     ; Tue May 17 08:58:31 2011 ;
+---------------+--------+--------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                              ;
+--------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+----------------------------------------------------+------------------------------------------------------+
; Clock Name                                       ; Type      ; Period ; Frequency ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source                                             ; Targets                                              ;
+--------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+----------------------------------------------------+------------------------------------------------------+
; clk_12                                           ; Base      ; 83.333 ; 12.0 MHz  ; 0.000 ; 41.666 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;                                                    ; { clk_12 }                                           ;
; clk_T1                                           ; Base      ; 66.667 ; 15.0 MHz  ; 0.000 ; 33.333 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;                                                    ; { clk_T1 }                                           ;
; pll0|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 20.833 ; 48.0 MHz  ; 1.001 ; 11.417 ; 50.00      ; 1         ; 4           ; 17.3  ;        ;           ;            ; false    ; clk_12 ; pll0|altpll_component|auto_generated|pll1|inclk[0] ; { pll0|altpll_component|auto_generated|pll1|clk[1] } ;
; spi_sck                                          ; Base      ; 33.333 ; 30.0 MHz  ; 0.000 ; 16.666 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;                                                    ; { spi_sck }                                          ;
+--------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+----------------------------------------------------+------------------------------------------------------+


+----------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                     ;
+------------+-----------------+--------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                       ; Note ;
+------------+-----------------+--------------------------------------------------+------+
; 170.3 MHz  ; 170.3 MHz       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;      ;
; 237.02 MHz ; 237.02 MHz      ; spi_sck                                          ;      ;
+------------+-----------------+--------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+---------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                       ;
+--------------------------------------------------+--------+---------------+
; Clock                                            ; Slack  ; End Point TNS ;
+--------------------------------------------------+--------+---------------+
; pll0|altpll_component|auto_generated|pll1|clk[1] ; 7.865  ; 0.000         ;
; spi_sck                                          ; 29.114 ; 0.000         ;
+--------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                       ;
+--------------------------------------------------+-------+---------------+
; Clock                                            ; Slack ; End Point TNS ;
+--------------------------------------------------+-------+---------------+
; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.160 ; 0.000         ;
; spi_sck                                          ; 0.436 ; 0.000         ;
+--------------------------------------------------+-------+---------------+


------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.


-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.


+---------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                         ;
+--------------------------------------------------+--------+---------------+
; Clock                                            ; Slack  ; End Point TNS ;
+--------------------------------------------------+--------+---------------+
; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.081 ; 0.000         ;
; spi_sck                                          ; 16.414 ; 0.000         ;
; clk_12                                           ; 41.557 ; 0.000         ;
; clk_T1                                           ; 63.542 ; 0.000         ;
+--------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'pll0|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                  ;
+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                             ; To Node                                                          ; Launch Clock                                     ; Latch Clock                                      ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+------------+------------+
; 7.865  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_exec                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.486     ; 2.067      ;
; 7.867  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_addr                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.486     ; 2.065      ;
; 7.879  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[11]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 2.501      ;
; 7.879  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[10]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 2.501      ;
; 7.879  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[3]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 2.501      ;
; 7.950  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_exec                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.486     ; 1.982      ;
; 7.952  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_addr                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.486     ; 1.980      ;
; 7.964  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[11]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 2.416      ;
; 7.964  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[10]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 2.416      ;
; 7.964  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[3]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.038     ; 2.416      ;
; 8.094  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[15]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.333      ;
; 8.094  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[14]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.333      ;
; 8.094  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[13]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.333      ;
; 8.094  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[12]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.333      ;
; 8.094  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[8]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.333      ;
; 8.094  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[2]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.333      ;
; 8.094  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[9]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.333      ;
; 8.094  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[1]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.333      ;
; 8.094  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[0]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.333      ;
; 8.094  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[4]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.333      ;
; 8.094  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[5]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.333      ;
; 8.094  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[7]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.333      ;
; 8.094  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[6]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.333      ;
; 8.179  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[15]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.248      ;
; 8.179  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[14]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.248      ;
; 8.179  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[13]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.248      ;
; 8.179  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[12]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.248      ;
; 8.179  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[8]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.248      ;
; 8.179  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[2]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.248      ;
; 8.179  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[9]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.248      ;
; 8.179  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[1]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.248      ;
; 8.179  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[0]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.248      ;
; 8.179  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[4]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.248      ;
; 8.179  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[5]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.248      ;
; 8.179  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[7]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.248      ;
; 8.179  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[6]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 2.248      ;
; 8.234  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[6] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.036     ; 2.148      ;
; 8.234  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[5] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.036     ; 2.148      ;
; 8.234  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[4] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.036     ; 2.148      ;
; 8.234  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[3] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.036     ; 2.148      ;
; 8.234  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[2] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.036     ; 2.148      ;
; 8.234  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.036     ; 2.148      ;
; 8.234  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[0] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.036     ; 2.148      ;
; 8.405  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[6] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.036     ; 1.977      ;
; 8.405  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[5] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.036     ; 1.977      ;
; 8.405  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[4] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.036     ; 1.977      ;
; 8.405  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[3] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.036     ; 1.977      ;
; 8.405  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[2] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.036     ; 1.977      ;
; 8.405  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.036     ; 1.977      ;
; 8.405  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[0] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.036     ; 1.977      ;
; 8.423  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[7] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.036     ; 1.959      ;
; 8.769  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[7] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.036     ; 1.613      ;
; 8.772  ; frontend:front|spi_slave:arm|rx_d_n[13]                                                                                                               ; frontend:front|spi_slave:arm|rx_data[13]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.009      ; 1.655      ;
; 8.802  ; frontend:front|spi_slave:arm|rx_d_n[9]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[9]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.442      ; 2.058      ;
; 9.147  ; frontend:front|spi_slave:arm|rx_d_n[7]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[7]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.440      ; 1.711      ;
; 9.200  ; frontend:front|spi_slave:arm|rx_d_n[12]                                                                                                               ; frontend:front|spi_slave:arm|rx_data[12]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.442      ; 1.660      ;
; 9.354  ; frontend:front|spi_slave:arm|tx_fetch_nn                                                                                                              ; frontend:front|spi_slave:arm|tx_fetched                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 1.029      ;
; 9.400  ; frontend:front|spi_slave:arm|rx_d_n[4]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[4]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.440      ; 1.458      ;
; 9.443  ; frontend:front|spi_slave:arm|rx_d_n[1]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[1]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.460      ; 1.435      ;
; 9.448  ; frontend:front|spi_slave:arm|rx_d_n[0]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[0]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.440      ; 1.410      ;
; 9.463  ; frontend:front|spi_slave:arm|rx_d_n[8]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[8]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.457      ; 1.412      ;
; 9.490  ; frontend:front|spi_slave:arm|tx_fetch_n                                                                                                               ; frontend:front|spi_slave:arm|tx_fetched                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.035     ; 0.893      ;
; 9.521  ; frontend:front|spi_slave:arm|rx_d_n[2]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[2]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.440      ; 1.337      ;
; 9.538  ; frontend:front|spi_slave:arm|rx_d_n[14]                                                                                                               ; frontend:front|spi_slave:arm|rx_data[14]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.442      ; 1.322      ;
; 9.587  ; frontend:front|spi_slave:arm|rx_d_n[6]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[6]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.440      ; 1.271      ;
; 9.594  ; frontend:front|spi_slave:arm|rx_d_n[5]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[5]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.440      ; 1.264      ;
; 9.743  ; frontend:front|spi_slave:arm|rx_d_n[11]                                                                                                               ; frontend:front|spi_slave:arm|rx_data[11]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.408      ; 1.083      ;
; 9.776  ; frontend:front|spi_slave:arm|rx_d_n[3]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[3]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.408      ; 1.050      ;
; 9.783  ; frontend:front|spi_slave:arm|rx_d_n[10]                                                                                                               ; frontend:front|spi_slave:arm|rx_data[10]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.410      ; 1.045      ;
; 9.801  ; frontend:front|spi_slave:arm|rx_d_n[15]                                                                                                               ; frontend:front|spi_slave:arm|rx_data[15]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.440      ; 1.057      ;
; 14.961 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[8]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.388     ; 5.485      ;
; 14.961 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[4]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.388     ; 5.485      ;
; 14.961 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[6]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.388     ; 5.485      ;
; 14.961 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[5]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.388     ; 5.485      ;
; 14.961 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[7]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.388     ; 5.485      ;
; 14.961 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[1]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.388     ; 5.485      ;
; 14.961 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[0]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.388     ; 5.485      ;
; 14.961 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[2]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.388     ; 5.485      ;
; 14.961 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[3]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.388     ; 5.485      ;
; 15.042 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[8]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.391     ; 5.401      ;
; 15.042 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[4]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.391     ; 5.401      ;
; 15.042 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[6]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.391     ; 5.401      ;
; 15.042 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[5]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.391     ; 5.401      ;
; 15.042 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[7]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.391     ; 5.401      ;
; 15.042 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[1]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.391     ; 5.401      ;
; 15.042 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[0]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.391     ; 5.401      ;
; 15.042 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[2]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.391     ; 5.401      ;
; 15.042 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[3]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.391     ; 5.401      ;
; 15.109 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[8]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.388     ; 5.337      ;
; 15.109 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[4]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.388     ; 5.337      ;
; 15.109 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[6]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.388     ; 5.337      ;
; 15.109 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[5]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.388     ; 5.337      ;
; 15.109 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[7]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.388     ; 5.337      ;
; 15.109 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[1]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.388     ; 5.337      ;
; 15.109 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[0]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.388     ; 5.337      ;
; 15.109 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[2]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.388     ; 5.337      ;
; 15.109 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[3]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.388     ; 5.337      ;
; 15.160 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[12] ; frontend:front|packetfifo:hkfifo|count[8]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.391     ; 5.283      ;
; 15.160 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[12] ; frontend:front|packetfifo:hkfifo|count[4]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.391     ; 5.283      ;
; 15.160 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[12] ; frontend:front|packetfifo:hkfifo|count[6]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.391     ; 5.283      ;
+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'spi_sck'                                                                                                                                                   ;
+--------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                           ; To Node                                             ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 29.114 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|miso                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.132     ; 3.958      ;
; 29.769 ; frontend:front|spi_slave:arm|tx_sr[14]              ; frontend:front|spi_slave:arm|miso                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.129     ; 3.306      ;
; 30.606 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 2.650      ;
; 30.606 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 2.650      ;
; 30.624 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 2.632      ;
; 30.624 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 2.632      ;
; 30.757 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 2.499      ;
; 30.757 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 2.499      ;
; 31.011 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 2.245      ;
; 31.011 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 2.245      ;
; 31.172 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 2.084      ;
; 31.190 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 2.066      ;
; 31.192 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[14]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.082     ; 2.060      ;
; 31.192 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[13]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.082     ; 2.060      ;
; 31.192 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[12]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.082     ; 2.060      ;
; 31.192 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[11]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.082     ; 2.060      ;
; 31.192 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[10]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.082     ; 2.060      ;
; 31.192 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[9]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.082     ; 2.060      ;
; 31.192 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[8]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.082     ; 2.060      ;
; 31.230 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[7]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.076     ; 2.028      ;
; 31.230 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[6]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.076     ; 2.028      ;
; 31.230 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[5]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.076     ; 2.028      ;
; 31.230 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[4]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.076     ; 2.028      ;
; 31.230 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.076     ; 2.028      ;
; 31.230 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[2]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.076     ; 2.028      ;
; 31.230 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[1]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.076     ; 2.028      ;
; 31.313 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.076     ; 1.945      ;
; 31.318 ; frontend:front|spi_slave:arm|tx_sr[7]               ; frontend:front|spi_slave:arm|tx_sr[8]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.085     ; 1.931      ;
; 31.323 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 1.933      ;
; 31.519 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 1.737      ;
; 31.545 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 1.711      ;
; 31.551 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 1.705      ;
; 31.747 ; frontend:front|spi_slave:arm|rx_sr[3]               ; frontend:front|spi_slave:arm|rx_sr[4]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.084     ; 1.503      ;
; 31.753 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 1.503      ;
; 31.782 ; frontend:front|spi_slave:arm|rx_sr[0]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.075     ; 1.477      ;
; 31.816 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[2]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 1.440      ;
; 31.882 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 1.374      ;
; 31.889 ; frontend:front|spi_slave:arm|rx_sr[0]               ; frontend:front|spi_slave:arm|rx_sr[1]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.076     ; 1.369      ;
; 31.900 ; frontend:front|spi_slave:arm|rx_sr[0]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 33.333       ; -0.075     ; 1.359      ;
; 31.904 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 1.352      ;
; 31.934 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 1.322      ;
; 31.941 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 1.315      ;
; 31.960 ; frontend:front|spi_slave:arm|tx_sr[0]               ; frontend:front|spi_slave:arm|tx_sr[1]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.295      ;
; 31.963 ; frontend:front|spi_slave:arm|tx_sr[1]               ; frontend:front|spi_slave:arm|tx_sr[2]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.292      ;
; 31.991 ; frontend:front|spi_slave:arm|rx_sr[11]              ; frontend:front|spi_slave:arm|rx_sr[12]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.264      ;
; 32.005 ; frontend:front|spi_slave:arm|tx_sr[12]              ; frontend:front|spi_slave:arm|tx_sr[13]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.250      ;
; 32.041 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_fetch               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 1.215      ;
; 32.041 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 1.215      ;
; 32.041 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 1.215      ;
; 32.126 ; frontend:front|spi_slave:arm|rx_sr[13]              ; frontend:front|spi_slave:arm|rx_sr[14]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.129      ;
; 32.136 ; frontend:front|spi_slave:arm|rx_sr[6]               ; frontend:front|spi_slave:arm|rx_sr[7]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.119      ;
; 32.138 ; frontend:front|spi_slave:arm|rx_sr[10]              ; frontend:front|spi_slave:arm|rx_sr[11]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.117      ;
; 32.157 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 1.099      ;
; 32.161 ; frontend:front|spi_slave:arm|tx_sr[10]              ; frontend:front|spi_slave:arm|tx_sr[11]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.094      ;
; 32.161 ; frontend:front|spi_slave:arm|tx_sr[8]               ; frontend:front|spi_slave:arm|tx_sr[9]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.094      ;
; 32.162 ; frontend:front|spi_slave:arm|tx_sr[13]              ; frontend:front|spi_slave:arm|tx_sr[14]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.093      ;
; 32.162 ; frontend:front|spi_slave:arm|tx_sr[2]               ; frontend:front|spi_slave:arm|tx_sr[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.093      ;
; 32.163 ; frontend:front|spi_slave:arm|tx_sr[9]               ; frontend:front|spi_slave:arm|tx_sr[10]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.092      ;
; 32.163 ; frontend:front|spi_slave:arm|tx_sr[6]               ; frontend:front|spi_slave:arm|tx_sr[7]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.092      ;
; 32.163 ; frontend:front|spi_slave:arm|tx_sr[5]               ; frontend:front|spi_slave:arm|tx_sr[6]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.092      ;
; 32.163 ; frontend:front|spi_slave:arm|tx_sr[3]               ; frontend:front|spi_slave:arm|tx_sr[4]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.092      ;
; 32.164 ; frontend:front|spi_slave:arm|tx_sr[11]              ; frontend:front|spi_slave:arm|tx_sr[12]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.091      ;
; 32.164 ; frontend:front|spi_slave:arm|tx_sr[4]               ; frontend:front|spi_slave:arm|tx_sr[5]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.091      ;
; 32.165 ; frontend:front|spi_slave:arm|rx_sr[14]              ; frontend:front|spi_slave:arm|rx_sr[15]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.080     ; 1.089      ;
; 32.187 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 1.069      ;
; 32.192 ; frontend:front|spi_slave:arm|rx_sr[9]               ; frontend:front|spi_slave:arm|rx_sr[10]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.063      ;
; 32.297 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[2]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 0.959      ;
; 32.298 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[1]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 0.958      ;
; 32.298 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 0.958      ;
; 32.321 ; frontend:front|spi_slave:arm|param                  ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 0.935      ;
; 32.323 ; frontend:front|spi_slave:arm|param                  ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 0.933      ;
; 32.332 ; frontend:front|spi_slave:arm|rx_sr[1]               ; frontend:front|spi_slave:arm|rx_sr[2]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 0.923      ;
; 32.335 ; frontend:front|spi_slave:arm|rx_sr[8]               ; frontend:front|spi_slave:arm|rx_sr[9]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 0.920      ;
; 32.337 ; frontend:front|spi_slave:arm|rx_sr[12]              ; frontend:front|spi_slave:arm|rx_sr[13]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 0.918      ;
; 32.346 ; frontend:front|spi_slave:arm|rx_sr[4]               ; frontend:front|spi_slave:arm|rx_sr[5]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 0.909      ;
; 32.347 ; frontend:front|spi_slave:arm|rx_sr[7]               ; frontend:front|spi_slave:arm|rx_sr[8]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 0.908      ;
; 32.347 ; frontend:front|spi_slave:arm|rx_sr[5]               ; frontend:front|spi_slave:arm|rx_sr[6]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 0.908      ;
; 32.349 ; frontend:front|spi_slave:arm|rx_sr[2]               ; frontend:front|spi_slave:arm|rx_sr[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 0.906      ;
; 32.397 ; frontend:front|spi_slave:arm|spi_timeout:tout|sclk2 ; frontend:front|spi_slave:arm|spi_timeout:tout|sclk2 ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 0.858      ;
; 32.398 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|frame[2]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 0.858      ;
; 32.398 ; frontend:front|spi_slave:arm|param                  ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 0.858      ;
; 32.398 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[1]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.078     ; 0.858      ;
+--------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'pll0|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                ;
+-------+------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                          ; To Node                                                                                                                                                           ; Launch Clock                                     ; Latch Clock                                      ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+------------+------------+
; 0.160 ; frontend:front|spi_slave:arm|rx_d_p[9]                                                                                             ; frontend:front|spi_slave:arm|rx_data[9]                                                                                                                           ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.581      ; 0.973      ;
; 0.165 ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[28]                                                                                      ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[28]                                                                                                                     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.566      ; 0.963      ;
; 0.166 ; frontend:front|spi_slave:arm|rx_d_p[13]                                                                                            ; frontend:front|spi_slave:arm|rx_data[13]                                                                                                                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.581      ; 0.979      ;
; 0.174 ; frontend:front|spi_slave:arm|rx_d_p[0]                                                                                             ; frontend:front|spi_slave:arm|rx_data[0]                                                                                                                           ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.580      ; 0.986      ;
; 0.296 ; cntr_array:cntrs|cntr_reg:cntr[2].c|latch[14]                                                                                      ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[14]                                                                                                                     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.528      ; 1.056      ;
; 0.307 ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[29]                                                                                      ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[29]                                                                                                                     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.566      ; 1.105      ;
; 0.308 ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[23]                                                                                      ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[23]                                                                                                                     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.566      ; 1.106      ;
; 0.310 ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[27]                                                                                      ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[27]                                                                                                                     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.566      ; 1.108      ;
; 0.311 ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[22]                                                                                      ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[22]                                                                                                                     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.566      ; 1.109      ;
; 0.332 ; frontend:front|spi_slave:arm|rx_d_p[4]                                                                                             ; frontend:front|spi_slave:arm|rx_data[4]                                                                                                                           ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.580      ; 1.144      ;
; 0.406 ; frontend:front|packetfifo:hkfifo|start                                                                                             ; frontend:front|packetfifo:hkfifo|search                                                                                                                           ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.567      ; 1.205      ;
; 0.410 ; frontend:front|spi_slave:arm|rx_d_p[14]                                                                                            ; frontend:front|spi_slave:arm|rx_data[14]                                                                                                                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.581      ; 1.223      ;
; 0.415 ; frontend:front|error_reg:master_errc|stat[4]                                                                                       ; frontend:front|error_reg:master_errc|stat[4]                                                                                                                      ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.415 ; frontend:front|packetfifo:hkfifo|search                                                                                            ; frontend:front|packetfifo:hkfifo|search                                                                                                                           ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.426 ; message:msg|tx_data[3]                                                                                                             ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram|ram_block1a0~porta_datain_reg0 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.179      ;
; 0.428 ; frontend:front|spi_slave:arm|rx_d_p[15]                                                                                            ; frontend:front|spi_slave:arm|rx_data[15]                                                                                                                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.580      ; 1.240      ;
; 0.433 ; frontend:front|spi_slave:arm|rx_d_p[7]                                                                                             ; frontend:front|spi_slave:arm|rx_data[7]                                                                                                                           ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.580      ; 1.245      ;
; 0.434 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|full_dff         ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|full_dff                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[3]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[3]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[8]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[8]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|t_shift[1]                                                                                                             ; message:msg|t_shift[1]                                                                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|t_shift[0]                                                                                                             ; message:msg|t_shift[0]                                                                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|t_shift[3]                                                                                                             ; message:msg|t_shift[3]                                                                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|crc_byte:crc_tx|bitcount[1]                                                                                            ; message:msg|crc_byte:crc_tx|bitcount[1]                                                                                                                           ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|crc_byte:crc_rx|bitcount[2]                                                                                            ; message:msg|crc_byte:crc_rx|bitcount[2]                                                                                                                           ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|crc_byte:crc_rx|bitcount[1]                                                                                            ; message:msg|crc_byte:crc_rx|bitcount[1]                                                                                                                           ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[1]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[1]                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[2]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[2]                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[5]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[5]                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[6]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[6]                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; frontend:front|error_reg:master_errc|stat[12]                                                                                      ; frontend:front|error_reg:master_errc|stat[12]                                                                                                                     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; frontend:front|error_reg:master_errc|stat[13]                                                                                      ; frontend:front|error_reg:master_errc|stat[13]                                                                                                                     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; push_msg_cnt[2]                                                                                                                    ; push_msg_cnt[2]                                                                                                                                                   ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[6]  ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[6]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[9]  ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[9]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]  ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[3]  ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[3]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|usedw_is_0_dff   ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|usedw_is_0_dff                                  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|uart:uart|uart_rx:rx1|attn                                                                                             ; message:msg|uart:uart|uart_rx:rx1|attn                                                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|uart:uart|uart_rx:rx2|attn                                                                                             ; message:msg|uart:uart|uart_rx:rx2|attn                                                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; frontend:front|error_reg:master_errc|stat[11]                                                                                      ; frontend:front|error_reg:master_errc|stat[11]                                                                                                                     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|msg_phase[3]                                                                                                           ; message:msg|msg_phase[3]                                                                                                                                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|uart:uart|uart_rx:rx1|brk                                                                                              ; message:msg|uart:uart|uart_rx:rx1|brk                                                                                                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|uart:uart|uart_rx:rx2|brk                                                                                              ; message:msg|uart:uart|uart_rx:rx2|brk                                                                                                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|uart:uart|uart_rx:rx1|busy                                                                                             ; message:msg|uart:uart|uart_rx:rx1|busy                                                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|uart:uart|uart_rx:rx1|clk1[1]                                                                                          ; message:msg|uart:uart|uart_rx:rx1|clk1[1]                                                                                                                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|uart:uart|uart_rx:rx1|clk1[3]                                                                                          ; message:msg|uart:uart|uart_rx:rx1|clk1[3]                                                                                                                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|uart:uart|uart_rx:rx1|clk1[2]                                                                                          ; message:msg|uart:uart|uart_rx:rx1|clk1[2]                                                                                                                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|uart:uart|uart_rx:rx2|clk1[3]                                                                                          ; message:msg|uart:uart|uart_rx:rx2|clk1[3]                                                                                                                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|uart:uart|uart_rx:rx2|clk1[2]                                                                                          ; message:msg|uart:uart|uart_rx:rx2|clk1[2]                                                                                                                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|uart:uart|uart_rx:rx2|clk1[1]                                                                                          ; message:msg|uart:uart|uart_rx:rx2|clk1[1]                                                                                                                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|uart:uart|baudgen:bgen|clk16div[3]                                                                                     ; message:msg|uart:uart|baudgen:bgen|clk16div[3]                                                                                                                    ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|uart:uart|baudgen:bgen|clk16div[2]                                                                                     ; message:msg|uart:uart|baudgen:bgen|clk16div[2]                                                                                                                    ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; message:msg|uart:uart|baudgen:bgen|clk16div[1]                                                                                     ; message:msg|uart:uart|baudgen:bgen|clk16div[1]                                                                                                                    ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; frontend:front|error_reg:master_errc|stat[0]                                                                                       ; frontend:front|error_reg:master_errc|stat[0]                                                                                                                      ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.434 ; frontend:front|error_reg:master_errc|stat[1]                                                                                       ; frontend:front|error_reg:master_errc|stat[1]                                                                                                                      ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.435 ; message:msg|uart:uart|uart_tx:tx|busy                                                                                              ; message:msg|uart:uart|uart_tx:tx|busy                                                                                                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; message:msg|uart:uart|uart_tx:tx|bc[1]                                                                                             ; message:msg|uart:uart|uart_tx:tx|bc[1]                                                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; message:msg|uart:uart|uart_tx:tx|bc[0]                                                                                             ; message:msg|uart:uart|uart_tx:tx|bc[0]                                                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; message:msg|uart:uart|uart_tx:tx|bc[3]                                                                                             ; message:msg|uart:uart|uart_tx:tx|bc[3]                                                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; message:msg|uart:uart|uart_tx:tx|bc[2]                                                                                             ; message:msg|uart:uart|uart_tx:tx|bc[2]                                                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|spi_slave:arm|tx_avail                                                                                              ; frontend:front|spi_slave:arm|tx_avail                                                                                                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]  ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[1]  ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[1]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[2]  ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[2]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[3]  ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[3]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[4]  ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[4]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[5]  ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[5]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[6]  ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[6]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[7]  ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[7]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[8]  ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[8]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[9]  ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[9]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[10] ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[10]                                ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|error_reg:master_errc|stat[14]                                                                                      ; frontend:front|error_reg:master_errc|stat[14]                                                                                                                     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|error_reg:master_errc|stat[15]                                                                                      ; frontend:front|error_reg:master_errc|stat[15]                                                                                                                     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[1]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[1]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[2]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[2]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[4]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[4]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[5]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[5]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[6]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[6]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[7]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[7]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[9]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[9]                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[10] ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[10]                                ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; message:msg|t_phase[1]                                                                                                             ; message:msg|t_phase[1]                                                                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; message:msg|t_phase[0]                                                                                                             ; message:msg|t_phase[0]                                                                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; message:msg|crc_byte:crc_tx|busy                                                                                                   ; message:msg|crc_byte:crc_tx|busy                                                                                                                                  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|full_dff                ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|full_dff                                               ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|dffe_af                               ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|dffe_af                                                              ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|cntl_reg:master_conf|stat[4]                                                                                        ; frontend:front|cntl_reg:master_conf|stat[4]                                                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|usedw_is_0_dff          ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|usedw_is_0_dff                                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|cntl_reg:master_conf|stat[3]                                                                                        ; frontend:front|cntl_reg:master_conf|stat[3]                                                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[0]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[0]                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[3]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[3]                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[4]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[4]                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[7]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[7]                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[8]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[8]                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[9]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[9]                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|cntl_reg:master_conf|stat[9]                                                                                        ; frontend:front|cntl_reg:master_conf|stat[9]                                                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
; 0.435 ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|full_dff         ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|full_dff                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.746      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'spi_sck'                                                                                                                                                   ;
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                           ; To Node                                             ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.436 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[1]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 0.746      ;
; 0.436 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|frame[2]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 0.746      ;
; 0.447 ; frontend:front|spi_slave:arm|spi_timeout:tout|sclk2 ; frontend:front|spi_slave:arm|spi_timeout:tout|sclk2 ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 0.758      ;
; 0.448 ; frontend:front|spi_slave:arm|param                  ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 0.758      ;
; 0.501 ; frontend:front|spi_slave:arm|param                  ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 0.811      ;
; 0.502 ; frontend:front|spi_slave:arm|param                  ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 0.812      ;
; 0.507 ; frontend:front|spi_slave:arm|rx_sr[2]               ; frontend:front|spi_slave:arm|rx_sr[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 0.818      ;
; 0.508 ; frontend:front|spi_slave:arm|rx_sr[7]               ; frontend:front|spi_slave:arm|rx_sr[8]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 0.819      ;
; 0.508 ; frontend:front|spi_slave:arm|rx_sr[5]               ; frontend:front|spi_slave:arm|rx_sr[6]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 0.819      ;
; 0.509 ; frontend:front|spi_slave:arm|rx_sr[4]               ; frontend:front|spi_slave:arm|rx_sr[5]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 0.820      ;
; 0.510 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[1]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 0.820      ;
; 0.510 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[2]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 0.820      ;
; 0.511 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 0.821      ;
; 0.516 ; frontend:front|spi_slave:arm|rx_sr[12]              ; frontend:front|spi_slave:arm|rx_sr[13]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 0.827      ;
; 0.517 ; frontend:front|spi_slave:arm|rx_sr[8]               ; frontend:front|spi_slave:arm|rx_sr[9]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 0.828      ;
; 0.520 ; frontend:front|spi_slave:arm|rx_sr[1]               ; frontend:front|spi_slave:arm|rx_sr[2]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 0.831      ;
; 0.631 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 0.941      ;
; 0.660 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 0.970      ;
; 0.680 ; frontend:front|spi_slave:arm|tx_sr[11]              ; frontend:front|spi_slave:arm|tx_sr[12]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 0.991      ;
; 0.681 ; frontend:front|spi_slave:arm|tx_sr[13]              ; frontend:front|spi_slave:arm|tx_sr[14]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 0.992      ;
; 0.681 ; frontend:front|spi_slave:arm|tx_sr[6]               ; frontend:front|spi_slave:arm|tx_sr[7]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 0.992      ;
; 0.681 ; frontend:front|spi_slave:arm|tx_sr[5]               ; frontend:front|spi_slave:arm|tx_sr[6]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 0.992      ;
; 0.682 ; frontend:front|spi_slave:arm|tx_sr[4]               ; frontend:front|spi_slave:arm|tx_sr[5]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 0.993      ;
; 0.682 ; frontend:front|spi_slave:arm|tx_sr[3]               ; frontend:front|spi_slave:arm|tx_sr[4]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 0.993      ;
; 0.682 ; frontend:front|spi_slave:arm|tx_sr[2]               ; frontend:front|spi_slave:arm|tx_sr[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 0.993      ;
; 0.683 ; frontend:front|spi_slave:arm|tx_sr[10]              ; frontend:front|spi_slave:arm|tx_sr[11]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 0.994      ;
; 0.683 ; frontend:front|spi_slave:arm|tx_sr[9]               ; frontend:front|spi_slave:arm|tx_sr[10]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 0.994      ;
; 0.683 ; frontend:front|spi_slave:arm|tx_sr[8]               ; frontend:front|spi_slave:arm|tx_sr[9]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 0.994      ;
; 0.692 ; frontend:front|spi_slave:arm|rx_sr[9]               ; frontend:front|spi_slave:arm|rx_sr[10]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 1.003      ;
; 0.705 ; frontend:front|spi_slave:arm|rx_sr[10]              ; frontend:front|spi_slave:arm|rx_sr[11]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 1.016      ;
; 0.706 ; frontend:front|spi_slave:arm|rx_sr[6]               ; frontend:front|spi_slave:arm|rx_sr[7]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 1.017      ;
; 0.713 ; frontend:front|spi_slave:arm|rx_sr[13]              ; frontend:front|spi_slave:arm|rx_sr[14]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 1.024      ;
; 0.716 ; frontend:front|spi_slave:arm|rx_sr[14]              ; frontend:front|spi_slave:arm|rx_sr[15]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 1.026      ;
; 0.751 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_fetch               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 1.061      ;
; 0.775 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 1.085      ;
; 0.780 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 1.090      ;
; 0.859 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 1.169      ;
; 0.861 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 1.171      ;
; 0.885 ; frontend:front|spi_slave:arm|tx_sr[12]              ; frontend:front|spi_slave:arm|tx_sr[13]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 1.196      ;
; 0.889 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 1.199      ;
; 0.893 ; frontend:front|spi_slave:arm|rx_sr[11]              ; frontend:front|spi_slave:arm|rx_sr[12]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 1.204      ;
; 0.926 ; frontend:front|spi_slave:arm|rx_sr[0]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 0.000        ; 0.082      ; 1.240      ;
; 0.930 ; frontend:front|spi_slave:arm|tx_sr[1]               ; frontend:front|spi_slave:arm|tx_sr[2]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 1.241      ;
; 0.933 ; frontend:front|spi_slave:arm|rx_sr[0]               ; frontend:front|spi_slave:arm|rx_sr[1]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.082      ; 1.247      ;
; 0.933 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 1.243      ;
; 0.934 ; frontend:front|spi_slave:arm|tx_sr[0]               ; frontend:front|spi_slave:arm|tx_sr[1]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.079      ; 1.245      ;
; 1.005 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[2]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 1.315      ;
; 1.012 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 1.322      ;
; 1.053 ; frontend:front|spi_slave:arm|rx_sr[0]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.082      ; 1.367      ;
; 1.096 ; frontend:front|spi_slave:arm|rx_sr[3]               ; frontend:front|spi_slave:arm|rx_sr[4]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.074      ; 1.402      ;
; 1.148 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 1.458      ;
; 1.195 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 1.505      ;
; 1.234 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 1.544      ;
; 1.381 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 1.691      ;
; 1.456 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 1.766      ;
; 1.458 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 1.768      ;
; 1.463 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.081      ; 1.776      ;
; 1.494 ; frontend:front|spi_slave:arm|tx_sr[7]               ; frontend:front|spi_slave:arm|tx_sr[8]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.073      ; 1.799      ;
; 1.549 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[7]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.081      ; 1.862      ;
; 1.549 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[6]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.081      ; 1.862      ;
; 1.549 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[5]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.081      ; 1.862      ;
; 1.549 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[4]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.081      ; 1.862      ;
; 1.549 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.081      ; 1.862      ;
; 1.549 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[2]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.081      ; 1.862      ;
; 1.549 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[1]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.081      ; 1.862      ;
; 1.587 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[14]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.075      ; 1.894      ;
; 1.587 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[13]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.075      ; 1.894      ;
; 1.587 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[12]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.075      ; 1.894      ;
; 1.587 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[11]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.075      ; 1.894      ;
; 1.587 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[10]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.075      ; 1.894      ;
; 1.587 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[9]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.075      ; 1.894      ;
; 1.587 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[8]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.075      ; 1.894      ;
; 1.875 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 2.185      ;
; 1.875 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 2.185      ;
; 2.181 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 2.491      ;
; 2.181 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 2.491      ;
; 2.256 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 2.566      ;
; 2.256 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 2.566      ;
; 2.258 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 2.568      ;
; 2.258 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.078      ; 2.568      ;
; 2.882 ; frontend:front|spi_slave:arm|tx_sr[14]              ; frontend:front|spi_slave:arm|miso                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.002      ; 3.030      ;
; 3.410 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|miso                   ; spi_sck      ; spi_sck     ; 0.000        ; -0.002     ; 3.554      ;
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'pll0|altpll_component|auto_generated|pll1|clk[1]'                                                                              ;
+--------+--------------+----------------+------------------+--------------------------------------------------+------------+------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                            ; Clock Edge ; Target                                         ;
+--------+--------------+----------------+------------------+--------------------------------------------------+------------+------------------------------------------------+
; 10.081 ; 10.301       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[16]  ;
; 10.081 ; 10.301       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[17]  ;
; 10.081 ; 10.301       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[18]  ;
; 10.081 ; 10.301       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[19]  ;
; 10.081 ; 10.301       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[21]  ;
; 10.081 ; 10.301       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[22]  ;
; 10.081 ; 10.301       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[23]  ;
; 10.081 ; 10.301       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[29]  ;
; 10.082 ; 10.302       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[13]  ;
; 10.082 ; 10.302       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[14]  ;
; 10.083 ; 10.303       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[13]  ;
; 10.083 ; 10.303       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[15]  ;
; 10.083 ; 10.303       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|wee        ;
; 10.083 ; 10.303       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|count[17] ;
; 10.083 ; 10.303       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|count[20] ;
; 10.083 ; 10.303       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|count[21] ;
; 10.083 ; 10.303       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|count[23] ;
; 10.083 ; 10.303       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|count[28] ;
; 10.083 ; 10.303       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|count[29] ;
; 10.083 ; 10.303       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|count[30] ;
; 10.083 ; 10.303       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|count[31] ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[19]  ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[20]  ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[21]  ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[23]  ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[24]  ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[25]  ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[26]  ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[27]  ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[31]  ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[3].c|count[25]  ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[3].c|count[30]  ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[3].c|count[31]  ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[16]  ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[20]  ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[21]  ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[30]  ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[31]  ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|rd[14]                        ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|conf_reg:spide_reg|stat[1]      ;
; 10.086 ; 10.306       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|conf_reg:spide_reg|stat[4]      ;
; 10.087 ; 10.307       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[22]  ;
; 10.087 ; 10.307       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[23]  ;
; 10.087 ; 10.307       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[27]  ;
; 10.087 ; 10.307       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[28]  ;
; 10.087 ; 10.307       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[29]  ;
; 10.088 ; 10.308       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[16]  ;
; 10.088 ; 10.308       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[17]  ;
; 10.088 ; 10.308       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[18]  ;
; 10.088 ; 10.308       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[22]  ;
; 10.088 ; 10.308       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[28]  ;
; 10.088 ; 10.308       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[29]  ;
; 10.088 ; 10.308       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[30]  ;
; 10.088 ; 10.308       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|conf_reg:hkhdrvreg|stat[3]      ;
; 10.088 ; 10.308       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|conf_reg:hkhdrvreg|stat[5]      ;
; 10.088 ; 10.308       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|conf_reg:hkhdrvreg|stat[7]      ;
; 10.088 ; 10.308       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; t_init                                         ;
; 10.089 ; 10.309       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[20]  ;
; 10.089 ; 10.309       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[24]  ;
; 10.089 ; 10.309       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[25]  ;
; 10.089 ; 10.309       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[26]  ;
; 10.089 ; 10.309       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[27]  ;
; 10.089 ; 10.309       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[28]  ;
; 10.089 ; 10.309       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[30]  ;
; 10.089 ; 10.309       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[31]  ;
; 10.089 ; 10.309       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|latch[16]  ;
; 10.089 ; 10.309       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|latch[17]  ;
; 10.089 ; 10.309       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|latch[19]  ;
; 10.089 ; 10.309       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|latch[20]  ;
; 10.089 ; 10.309       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|latch[23]  ;
; 10.089 ; 10.309       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|latch[28]  ;
; 10.089 ; 10.309       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; message:msg|timeout_ctr[15]                    ;
; 10.089 ; 10.309       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; message:msg|timeout_ctr[16]                    ;
; 10.089 ; 10.309       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; message:msg|timeout_ctr[17]                    ;
; 10.090 ; 10.310       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[16]  ;
; 10.090 ; 10.310       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[17]  ;
; 10.090 ; 10.310       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[18]  ;
; 10.090 ; 10.310       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[19]  ;
; 10.090 ; 10.310       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[21]  ;
; 10.090 ; 10.310       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[22]  ;
; 10.090 ; 10.310       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[23]  ;
; 10.090 ; 10.310       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[29]  ;
; 10.090 ; 10.310       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[18]  ;
; 10.090 ; 10.310       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[21]  ;
; 10.090 ; 10.310       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[22]  ;
; 10.090 ; 10.310       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[24]  ;
; 10.090 ; 10.310       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[25]  ;
; 10.090 ; 10.310       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[26]  ;
; 10.090 ; 10.310       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[29]  ;
; 10.090 ; 10.310       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[30]  ;
; 10.090 ; 10.310       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[31]  ;
; 10.091 ; 10.311       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[20]  ;
; 10.091 ; 10.311       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[24]  ;
; 10.091 ; 10.311       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[25]  ;
; 10.091 ; 10.311       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[26]  ;
; 10.091 ; 10.311       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[27]  ;
; 10.091 ; 10.311       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[28]  ;
; 10.091 ; 10.311       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[30]  ;
; 10.091 ; 10.311       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[31]  ;
; 10.091 ; 10.311       ; 0.220          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|rx_data[10]       ;
+--------+--------------+----------------+------------------+--------------------------------------------------+------------+------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'spi_sck'                                                                                   ;
+--------+--------------+----------------+------------------+---------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+---------+------------+-----------------------------------------------------+
; 16.414 ; 16.602       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|addr                   ;
; 16.414 ; 16.602       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[0]               ;
; 16.414 ; 16.602       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[1]               ;
; 16.414 ; 16.602       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[2]               ;
; 16.414 ; 16.602       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[3]               ;
; 16.414 ; 16.602       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|last                   ;
; 16.414 ; 16.602       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|param                  ;
; 16.414 ; 16.602       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_fetch               ;
; 16.414 ; 16.602       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|verylast               ;
; 16.415 ; 16.603       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[1]               ;
; 16.415 ; 16.603       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[2]               ;
; 16.415 ; 16.603       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[3]               ;
; 16.415 ; 16.603       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|spi_timeout:tout|sclk2 ;
; 16.415 ; 16.603       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[0]               ;
; 16.415 ; 16.603       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[1]               ;
; 16.415 ; 16.603       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[2]               ;
; 16.415 ; 16.603       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[3]               ;
; 16.415 ; 16.603       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[4]               ;
; 16.415 ; 16.603       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[5]               ;
; 16.415 ; 16.603       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[6]               ;
; 16.415 ; 16.603       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[7]               ;
; 16.416 ; 16.604       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[0]               ;
; 16.416 ; 16.604       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[15]              ;
; 16.416 ; 16.604       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[10]              ;
; 16.416 ; 16.604       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[11]              ;
; 16.416 ; 16.604       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[12]              ;
; 16.416 ; 16.604       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[13]              ;
; 16.416 ; 16.604       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[14]              ;
; 16.416 ; 16.604       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[8]               ;
; 16.416 ; 16.604       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[9]               ;
; 16.417 ; 16.605       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[10]              ;
; 16.417 ; 16.605       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[11]              ;
; 16.417 ; 16.605       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[12]              ;
; 16.417 ; 16.605       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[13]              ;
; 16.417 ; 16.605       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[14]              ;
; 16.417 ; 16.605       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[4]               ;
; 16.417 ; 16.605       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[5]               ;
; 16.417 ; 16.605       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[6]               ;
; 16.417 ; 16.605       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[7]               ;
; 16.417 ; 16.605       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[8]               ;
; 16.417 ; 16.605       ; 0.188          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[9]               ;
; 16.477 ; 16.635       ; 0.158          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|miso                   ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|addr                   ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[0]               ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[1]               ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[2]               ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[3]               ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|last                   ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|param                  ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[0]               ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[10]              ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[11]              ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[12]              ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[13]              ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[14]              ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[15]              ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[4]               ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[5]               ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[6]               ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[7]               ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[8]               ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[9]               ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_fetch               ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[10]              ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[11]              ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[12]              ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[13]              ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[14]              ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[8]               ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[9]               ;
; 16.507 ; 16.727       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|verylast               ;
; 16.508 ; 16.728       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[1]               ;
; 16.508 ; 16.728       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[2]               ;
; 16.508 ; 16.728       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[3]               ;
; 16.508 ; 16.728       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|spi_timeout:tout|sclk2 ;
; 16.508 ; 16.728       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[0]               ;
; 16.508 ; 16.728       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[1]               ;
; 16.508 ; 16.728       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[2]               ;
; 16.508 ; 16.728       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[3]               ;
; 16.508 ; 16.728       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[4]               ;
; 16.508 ; 16.728       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[5]               ;
; 16.508 ; 16.728       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[6]               ;
; 16.508 ; 16.728       ; 0.220          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[7]               ;
; 16.543 ; 16.696       ; 0.153          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|miso                   ;
; 16.623 ; 16.623       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|addr|clk                                  ;
; 16.623 ; 16.623       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|frame[0]|clk                              ;
; 16.623 ; 16.623       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|frame[1]|clk                              ;
; 16.623 ; 16.623       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|frame[2]|clk                              ;
; 16.623 ; 16.623       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|frame[3]|clk                              ;
; 16.623 ; 16.623       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|last|clk                                  ;
; 16.623 ; 16.623       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|param|clk                                 ;
; 16.623 ; 16.623       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|tx_fetch|clk                              ;
; 16.623 ; 16.623       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|verylast|clk                              ;
; 16.624 ; 16.624       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|rx_sr[1]|clk                              ;
; 16.624 ; 16.624       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|rx_sr[2]|clk                              ;
; 16.624 ; 16.624       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|rx_sr[3]|clk                              ;
; 16.624 ; 16.624       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|tout|sclk2|clk                            ;
; 16.624 ; 16.624       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|tx_sr[0]|clk                              ;
; 16.624 ; 16.624       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|tx_sr[1]|clk                              ;
; 16.624 ; 16.624       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|tx_sr[2]|clk                              ;
+--------+--------------+----------------+------------------+---------+------------+-----------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'clk_12'                                                                                          ;
+--------+--------------+----------------+------------------+--------+------------+------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target                                                     ;
+--------+--------------+----------------+------------------+--------+------------+------------------------------------------------------------+
; 41.557 ; 41.557       ; 0.000          ; High Pulse Width ; clk_12 ; Rise       ; pll0|altpll_component|auto_generated|pll1|inclk[0]         ;
; 41.568 ; 41.568       ; 0.000          ; High Pulse Width ; clk_12 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1]           ;
; 41.568 ; 41.568       ; 0.000          ; High Pulse Width ; clk_12 ; Rise       ; pll0|altpll_component|auto_generated|pll1|observablevcoout ;
; 41.590 ; 41.590       ; 0.000          ; High Pulse Width ; clk_12 ; Rise       ; clk_12~input|o                                             ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clk_12 ; Rise       ; clk_12~input|i                                             ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clk_12 ; Rise       ; clk_12~input|i                                             ;
; 41.741 ; 41.741       ; 0.000          ; Low Pulse Width  ; clk_12 ; Rise       ; clk_12~input|o                                             ;
; 41.760 ; 41.760       ; 0.000          ; Low Pulse Width  ; clk_12 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1]           ;
; 41.760 ; 41.760       ; 0.000          ; Low Pulse Width  ; clk_12 ; Rise       ; pll0|altpll_component|auto_generated|pll1|observablevcoout ;
; 41.773 ; 41.773       ; 0.000          ; Low Pulse Width  ; clk_12 ; Rise       ; pll0|altpll_component|auto_generated|pll1|inclk[0]         ;
; 80.208 ; 83.333       ; 3.125          ; Port Rate        ; clk_12 ; Rise       ; clk_12                                                     ;
+--------+--------------+----------------+------------------+--------+------------+------------------------------------------------------------+


+-----------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'clk_T1'                               ;
+--------+--------------+----------------+-----------+--------+------------+--------+
; Slack  ; Actual Width ; Required Width ; Type      ; Clock  ; Clock Edge ; Target ;
+--------+--------------+----------------+-----------+--------+------------+--------+
; 63.542 ; 66.667       ; 3.125          ; Port Rate ; clk_T1 ; Rise       ; clk_T1 ;
+--------+--------------+----------------+-----------+--------+------------+--------+


+---------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                             ;
+-----------+------------+--------+-------+------------+--------------------------------------------------+
; Data Port ; Clock Port ; Rise   ; Fall  ; Clock Edge ; Clock Reference                                  ;
+-----------+------------+--------+-------+------------+--------------------------------------------------+
; Rx[*]     ; clk_12     ; -0.036 ; 0.265 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Rx[2]    ; clk_12     ; -0.308 ; 0.027 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Rx[3]    ; clk_12     ; -0.036 ; 0.265 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; spi_mosi  ; spi_sck    ; 0.335  ; 0.370 ; Fall       ; spi_sck                                          ;
+-----------+------------+--------+-------+------------+--------------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                             ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                  ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; Rx[*]     ; clk_12     ; 1.126 ; 0.804 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Rx[2]    ; clk_12     ; 1.126 ; 0.804 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Rx[3]    ; clk_12     ; 0.864 ; 0.575 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; spi_mosi  ; spi_sck    ; 0.132 ; 0.110 ; Fall       ; spi_sck                                          ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+


+------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                      ;
+-------------+------------+--------+--------+------------+--------------------------------------------------+
; Data Port   ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                  ;
+-------------+------------+--------+--------+------------+--------------------------------------------------+
; Tx[*]       ; clk_12     ; 15.858 ; 15.846 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Tx[1]      ; clk_12     ; 14.036 ; 13.764 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Tx[2]      ; clk_12     ; 15.858 ; 15.846 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; attn        ; clk_12     ; 15.207 ; 14.891 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; spi_miso    ; spi_sck    ; 8.307  ; 8.284  ; Fall       ; spi_sck                                          ;
; spi_miso(n) ; spi_sck    ; 8.284  ; 8.307  ; Fall       ; spi_sck                                          ;
+-------------+------------+--------+--------+------------+--------------------------------------------------+


+------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                              ;
+-------------+------------+--------+--------+------------+--------------------------------------------------+
; Data Port   ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                  ;
+-------------+------------+--------+--------+------------+--------------------------------------------------+
; Tx[*]       ; clk_12     ; 11.529 ; 11.356 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Tx[1]      ; clk_12     ; 11.529 ; 11.356 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Tx[2]      ; clk_12     ; 13.056 ; 13.041 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; attn        ; clk_12     ; 13.823 ; 13.522 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; spi_miso    ; spi_sck    ; 8.187  ; 8.165  ; Fall       ; spi_sck                                          ;
; spi_miso(n) ; spi_sck    ; 8.165  ; 8.187  ; Fall       ; spi_sck                                          ;
+-------------+------------+--------+--------+------------+--------------------------------------------------+


+------------------------------------------------------+
; Propagation Delay                                    ;
+------------+-------------+--------+----+----+--------+
; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
+------------+-------------+--------+----+----+--------+
; Rx[2]      ; Tx[1]       ; 9.997  ;    ;    ; 10.085 ;
; Rx[3]      ; Tx[2]       ; 12.040 ;    ;    ; 12.227 ;
+------------+-------------+--------+----+----+--------+


+------------------------------------------------------+
; Minimum Propagation Delay                            ;
+------------+-------------+--------+----+----+--------+
; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
+------------+-------------+--------+----+----+--------+
; Rx[2]      ; Tx[1]       ; 9.693  ;    ;    ; 9.769  ;
; Rx[3]      ; Tx[2]       ; 11.735 ;    ;    ; 11.918 ;
+------------+-------------+--------+----+----+--------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                      ;
+------------+-----------------+--------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                       ; Note ;
+------------+-----------------+--------------------------------------------------+------+
; 183.22 MHz ; 183.22 MHz      ; pll0|altpll_component|auto_generated|pll1|clk[1] ;      ;
; 253.29 MHz ; 253.29 MHz      ; spi_sck                                          ;      ;
+------------+-----------------+--------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+---------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                        ;
+--------------------------------------------------+--------+---------------+
; Clock                                            ; Slack  ; End Point TNS ;
+--------------------------------------------------+--------+---------------+
; pll0|altpll_component|auto_generated|pll1|clk[1] ; 8.077  ; 0.000         ;
; spi_sck                                          ; 29.385 ; 0.000         ;
+--------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                        ;
+--------------------------------------------------+-------+---------------+
; Clock                                            ; Slack ; End Point TNS ;
+--------------------------------------------------+-------+---------------+
; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.113 ; 0.000         ;
; spi_sck                                          ; 0.386 ; 0.000         ;
+--------------------------------------------------+-------+---------------+


-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+---------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                          ;
+--------------------------------------------------+--------+---------------+
; Clock                                            ; Slack  ; End Point TNS ;
+--------------------------------------------------+--------+---------------+
; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.058 ; 0.000         ;
; spi_sck                                          ; 16.406 ; 0.000         ;
; clk_12                                           ; 41.567 ; 0.000         ;
; clk_T1                                           ; 63.542 ; 0.000         ;
+--------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'pll0|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                   ;
+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                             ; To Node                                                          ; Launch Clock                                     ; Latch Clock                                      ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+------------+------------+
; 8.077  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_exec                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.408     ; 1.934      ;
; 8.078  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_addr                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.408     ; 1.933      ;
; 8.090  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[11]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.014      ; 2.343      ;
; 8.090  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[10]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.014      ; 2.343      ;
; 8.090  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[3]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.014      ; 2.343      ;
; 8.156  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_exec                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.408     ; 1.855      ;
; 8.157  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_addr                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.408     ; 1.854      ;
; 8.169  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[11]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.014      ; 2.264      ;
; 8.169  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[10]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.014      ; 2.264      ;
; 8.169  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[3]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.014      ; 2.264      ;
; 8.281  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[15]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.192      ;
; 8.281  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[14]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.192      ;
; 8.281  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[13]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.192      ;
; 8.281  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[12]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.192      ;
; 8.281  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[8]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.192      ;
; 8.281  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[2]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.192      ;
; 8.281  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[9]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.192      ;
; 8.281  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[1]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.192      ;
; 8.281  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[0]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.192      ;
; 8.281  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[4]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.192      ;
; 8.281  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[5]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.192      ;
; 8.281  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[7]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.192      ;
; 8.281  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[6]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.192      ;
; 8.360  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[15]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.113      ;
; 8.360  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[14]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.113      ;
; 8.360  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[13]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.113      ;
; 8.360  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[12]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.113      ;
; 8.360  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[8]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.113      ;
; 8.360  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[2]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.113      ;
; 8.360  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[9]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.113      ;
; 8.360  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[1]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.113      ;
; 8.360  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[0]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.113      ;
; 8.360  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[4]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.113      ;
; 8.360  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[5]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.113      ;
; 8.360  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[7]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.113      ;
; 8.360  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[6]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 2.113      ;
; 8.436  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[6] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.015     ; 1.968      ;
; 8.436  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[5] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.015     ; 1.968      ;
; 8.436  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[4] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.015     ; 1.968      ;
; 8.436  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[3] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.015     ; 1.968      ;
; 8.436  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[2] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.015     ; 1.968      ;
; 8.436  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.015     ; 1.968      ;
; 8.436  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[0] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.015     ; 1.968      ;
; 8.580  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[6] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.015     ; 1.824      ;
; 8.580  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[5] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.015     ; 1.824      ;
; 8.580  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[4] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.015     ; 1.824      ;
; 8.580  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[3] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.015     ; 1.824      ;
; 8.580  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[2] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.015     ; 1.824      ;
; 8.580  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.015     ; 1.824      ;
; 8.580  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[0] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.015     ; 1.824      ;
; 8.612  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[7] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.016     ; 1.791      ;
; 8.890  ; frontend:front|spi_slave:arm|rx_d_n[9]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[9]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.433      ; 1.962      ;
; 8.895  ; frontend:front|spi_slave:arm|rx_d_n[13]                                                                                                               ; frontend:front|spi_slave:arm|rx_data[13]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.054      ; 1.578      ;
; 8.906  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[7] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.016     ; 1.497      ;
; 9.209  ; frontend:front|spi_slave:arm|rx_d_n[7]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[7]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.430      ; 1.640      ;
; 9.277  ; frontend:front|spi_slave:arm|rx_d_n[12]                                                                                                               ; frontend:front|spi_slave:arm|rx_data[12]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.433      ; 1.575      ;
; 9.464  ; frontend:front|spi_slave:arm|tx_fetch_nn                                                                                                              ; frontend:front|spi_slave:arm|tx_fetched                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.015     ; 0.940      ;
; 9.503  ; frontend:front|spi_slave:arm|rx_d_n[1]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[1]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.448      ; 1.364      ;
; 9.511  ; frontend:front|spi_slave:arm|rx_d_n[4]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[4]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.430      ; 1.338      ;
; 9.517  ; frontend:front|spi_slave:arm|rx_d_n[8]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[8]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.444      ; 1.346      ;
; 9.561  ; frontend:front|spi_slave:arm|rx_d_n[0]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[0]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.430      ; 1.288      ;
; 9.563  ; frontend:front|spi_slave:arm|rx_d_n[2]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[2]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.430      ; 1.286      ;
; 9.593  ; frontend:front|spi_slave:arm|rx_d_n[14]                                                                                                               ; frontend:front|spi_slave:arm|rx_data[14]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.433      ; 1.259      ;
; 9.599  ; frontend:front|spi_slave:arm|tx_fetch_n                                                                                                               ; frontend:front|spi_slave:arm|tx_fetched                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.015     ; 0.805      ;
; 9.667  ; frontend:front|spi_slave:arm|rx_d_n[6]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[6]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.430      ; 1.182      ;
; 9.672  ; frontend:front|spi_slave:arm|rx_d_n[5]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[5]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.430      ; 1.177      ;
; 9.794  ; frontend:front|spi_slave:arm|rx_d_n[11]                                                                                                               ; frontend:front|spi_slave:arm|rx_data[11]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.403      ; 1.028      ;
; 9.830  ; frontend:front|spi_slave:arm|rx_d_n[3]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[3]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.403      ; 0.992      ;
; 9.834  ; frontend:front|spi_slave:arm|rx_d_n[10]                                                                                                               ; frontend:front|spi_slave:arm|rx_data[10]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.404      ; 0.989      ;
; 9.854  ; frontend:front|spi_slave:arm|rx_d_n[15]                                                                                                               ; frontend:front|spi_slave:arm|rx_data[15]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.430      ; 0.995      ;
; 15.375 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[8]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.339     ; 5.121      ;
; 15.375 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[4]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.339     ; 5.121      ;
; 15.375 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[6]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.339     ; 5.121      ;
; 15.375 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[5]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.339     ; 5.121      ;
; 15.375 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[7]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.339     ; 5.121      ;
; 15.375 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[1]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.339     ; 5.121      ;
; 15.375 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[0]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.339     ; 5.121      ;
; 15.375 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[2]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.339     ; 5.121      ;
; 15.375 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[3]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.339     ; 5.121      ;
; 15.435 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[8]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.342     ; 5.058      ;
; 15.435 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[4]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.342     ; 5.058      ;
; 15.435 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[6]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.342     ; 5.058      ;
; 15.435 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[5]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.342     ; 5.058      ;
; 15.435 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[7]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.342     ; 5.058      ;
; 15.435 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[1]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.342     ; 5.058      ;
; 15.435 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[0]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.342     ; 5.058      ;
; 15.435 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[2]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.342     ; 5.058      ;
; 15.435 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[3]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.342     ; 5.058      ;
; 15.496 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[8]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.339     ; 5.000      ;
; 15.496 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[4]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.339     ; 5.000      ;
; 15.496 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[6]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.339     ; 5.000      ;
; 15.496 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[5]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.339     ; 5.000      ;
; 15.496 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[7]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.339     ; 5.000      ;
; 15.496 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[1]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.339     ; 5.000      ;
; 15.496 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[0]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.339     ; 5.000      ;
; 15.496 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[2]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.339     ; 5.000      ;
; 15.496 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[3]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.339     ; 5.000      ;
; 15.546 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[12] ; frontend:front|packetfifo:hkfifo|count[8]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.341     ; 4.948      ;
; 15.546 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[12] ; frontend:front|packetfifo:hkfifo|count[4]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.341     ; 4.948      ;
; 15.546 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[12] ; frontend:front|packetfifo:hkfifo|count[6]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.341     ; 4.948      ;
+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'spi_sck'                                                                                                                                                    ;
+--------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                           ; To Node                                             ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 29.385 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|miso                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.102     ; 3.722      ;
; 29.961 ; frontend:front|spi_slave:arm|tx_sr[14]              ; frontend:front|spi_slave:arm|miso                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.098     ; 3.150      ;
; 30.856 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 2.411      ;
; 30.856 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 2.411      ;
; 30.863 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 2.404      ;
; 30.863 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 2.404      ;
; 30.978 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 2.289      ;
; 30.978 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 2.289      ;
; 31.208 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 2.059      ;
; 31.208 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 2.059      ;
; 31.333 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[14]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.072     ; 1.930      ;
; 31.333 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[13]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.072     ; 1.930      ;
; 31.333 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[12]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.072     ; 1.930      ;
; 31.333 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[11]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.072     ; 1.930      ;
; 31.333 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[10]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.072     ; 1.930      ;
; 31.333 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[9]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.072     ; 1.930      ;
; 31.333 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[8]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.072     ; 1.930      ;
; 31.368 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[7]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.066     ; 1.901      ;
; 31.368 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[6]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.066     ; 1.901      ;
; 31.368 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[5]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.066     ; 1.901      ;
; 31.368 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[4]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.066     ; 1.901      ;
; 31.368 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.066     ; 1.901      ;
; 31.368 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[2]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.066     ; 1.901      ;
; 31.368 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[1]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.066     ; 1.901      ;
; 31.389 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.878      ;
; 31.407 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.860      ;
; 31.433 ; frontend:front|spi_slave:arm|tx_sr[7]               ; frontend:front|spi_slave:arm|tx_sr[8]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.075     ; 1.827      ;
; 31.489 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.065     ; 1.781      ;
; 31.521 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.746      ;
; 31.697 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.570      ;
; 31.715 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.552      ;
; 31.724 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.543      ;
; 31.825 ; frontend:front|spi_slave:arm|rx_sr[3]               ; frontend:front|spi_slave:arm|rx_sr[4]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.073     ; 1.437      ;
; 31.868 ; frontend:front|spi_slave:arm|rx_sr[0]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.064     ; 1.403      ;
; 31.895 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.372      ;
; 31.918 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[2]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.349      ;
; 31.957 ; frontend:front|spi_slave:arm|rx_sr[0]               ; frontend:front|spi_slave:arm|rx_sr[1]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.065     ; 1.313      ;
; 31.968 ; frontend:front|spi_slave:arm|rx_sr[0]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 33.333       ; -0.064     ; 1.303      ;
; 32.002 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.265      ;
; 32.050 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.217      ;
; 32.057 ; frontend:front|spi_slave:arm|tx_sr[0]               ; frontend:front|spi_slave:arm|tx_sr[1]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.069     ; 1.209      ;
; 32.058 ; frontend:front|spi_slave:arm|tx_sr[1]               ; frontend:front|spi_slave:arm|tx_sr[2]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.069     ; 1.208      ;
; 32.077 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.190      ;
; 32.085 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.182      ;
; 32.101 ; frontend:front|spi_slave:arm|rx_sr[11]              ; frontend:front|spi_slave:arm|rx_sr[12]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.166      ;
; 32.108 ; frontend:front|spi_slave:arm|tx_sr[12]              ; frontend:front|spi_slave:arm|tx_sr[13]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.159      ;
; 32.173 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.094      ;
; 32.174 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.093      ;
; 32.175 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_fetch               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.092      ;
; 32.232 ; frontend:front|spi_slave:arm|rx_sr[13]              ; frontend:front|spi_slave:arm|rx_sr[14]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.035      ;
; 32.239 ; frontend:front|spi_slave:arm|rx_sr[14]              ; frontend:front|spi_slave:arm|rx_sr[15]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.069     ; 1.027      ;
; 32.241 ; frontend:front|spi_slave:arm|rx_sr[6]               ; frontend:front|spi_slave:arm|rx_sr[7]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.026      ;
; 32.242 ; frontend:front|spi_slave:arm|rx_sr[10]              ; frontend:front|spi_slave:arm|rx_sr[11]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.025      ;
; 32.262 ; frontend:front|spi_slave:arm|tx_sr[10]              ; frontend:front|spi_slave:arm|tx_sr[11]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.005      ;
; 32.262 ; frontend:front|spi_slave:arm|tx_sr[2]               ; frontend:front|spi_slave:arm|tx_sr[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.069     ; 1.004      ;
; 32.263 ; frontend:front|spi_slave:arm|tx_sr[13]              ; frontend:front|spi_slave:arm|tx_sr[14]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.004      ;
; 32.263 ; frontend:front|spi_slave:arm|tx_sr[8]               ; frontend:front|spi_slave:arm|tx_sr[9]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.004      ;
; 32.263 ; frontend:front|spi_slave:arm|tx_sr[6]               ; frontend:front|spi_slave:arm|tx_sr[7]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.069     ; 1.003      ;
; 32.263 ; frontend:front|spi_slave:arm|tx_sr[5]               ; frontend:front|spi_slave:arm|tx_sr[6]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.069     ; 1.003      ;
; 32.263 ; frontend:front|spi_slave:arm|tx_sr[3]               ; frontend:front|spi_slave:arm|tx_sr[4]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.069     ; 1.003      ;
; 32.264 ; frontend:front|spi_slave:arm|tx_sr[9]               ; frontend:front|spi_slave:arm|tx_sr[10]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.003      ;
; 32.264 ; frontend:front|spi_slave:arm|tx_sr[4]               ; frontend:front|spi_slave:arm|tx_sr[5]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.069     ; 1.002      ;
; 32.266 ; frontend:front|spi_slave:arm|tx_sr[11]              ; frontend:front|spi_slave:arm|tx_sr[12]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.001      ;
; 32.266 ; frontend:front|spi_slave:arm|rx_sr[9]               ; frontend:front|spi_slave:arm|rx_sr[10]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.001      ;
; 32.266 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 1.001      ;
; 32.291 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 0.976      ;
; 32.395 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[2]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 0.872      ;
; 32.397 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[1]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 0.870      ;
; 32.397 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 0.870      ;
; 32.418 ; frontend:front|spi_slave:arm|param                  ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 0.849      ;
; 32.420 ; frontend:front|spi_slave:arm|param                  ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 0.847      ;
; 32.435 ; frontend:front|spi_slave:arm|rx_sr[1]               ; frontend:front|spi_slave:arm|rx_sr[2]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 0.832      ;
; 32.439 ; frontend:front|spi_slave:arm|rx_sr[8]               ; frontend:front|spi_slave:arm|rx_sr[9]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 0.828      ;
; 32.440 ; frontend:front|spi_slave:arm|rx_sr[12]              ; frontend:front|spi_slave:arm|rx_sr[13]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 0.827      ;
; 32.448 ; frontend:front|spi_slave:arm|rx_sr[4]               ; frontend:front|spi_slave:arm|rx_sr[5]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 0.819      ;
; 32.449 ; frontend:front|spi_slave:arm|rx_sr[7]               ; frontend:front|spi_slave:arm|rx_sr[8]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 0.818      ;
; 32.449 ; frontend:front|spi_slave:arm|rx_sr[5]               ; frontend:front|spi_slave:arm|rx_sr[6]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 0.818      ;
; 32.451 ; frontend:front|spi_slave:arm|rx_sr[2]               ; frontend:front|spi_slave:arm|rx_sr[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 0.816      ;
; 32.497 ; frontend:front|spi_slave:arm|spi_timeout:tout|sclk2 ; frontend:front|spi_slave:arm|spi_timeout:tout|sclk2 ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 0.770      ;
; 32.497 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|frame[2]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 0.770      ;
; 32.497 ; frontend:front|spi_slave:arm|param                  ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 0.770      ;
; 32.497 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[1]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.068     ; 0.770      ;
+--------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'pll0|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                  ;
+-------+------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                          ; To Node                                                                                                                            ; Launch Clock                                     ; Latch Clock                                      ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+------------+------------+
; 0.113 ; frontend:front|spi_slave:arm|rx_d_p[9]                                                                                             ; frontend:front|spi_slave:arm|rx_data[9]                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.543      ; 0.871      ;
; 0.118 ; frontend:front|spi_slave:arm|rx_d_p[13]                                                                                            ; frontend:front|spi_slave:arm|rx_data[13]                                                                                           ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.543      ; 0.876      ;
; 0.131 ; frontend:front|spi_slave:arm|rx_d_p[0]                                                                                             ; frontend:front|spi_slave:arm|rx_data[0]                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.541      ; 0.887      ;
; 0.146 ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[28]                                                                                      ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[28]                                                                                      ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.529      ; 0.890      ;
; 0.271 ; cntr_array:cntrs|cntr_reg:cntr[2].c|latch[14]                                                                                      ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[14]                                                                                      ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.489      ; 0.975      ;
; 0.276 ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[29]                                                                                      ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[29]                                                                                      ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.529      ; 1.020      ;
; 0.278 ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[23]                                                                                      ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[23]                                                                                      ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.529      ; 1.022      ;
; 0.281 ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[27]                                                                                      ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[27]                                                                                      ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.529      ; 1.025      ;
; 0.282 ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[22]                                                                                      ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[22]                                                                                      ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.529      ; 1.026      ;
; 0.299 ; frontend:front|spi_slave:arm|rx_d_p[4]                                                                                             ; frontend:front|spi_slave:arm|rx_data[4]                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.541      ; 1.055      ;
; 0.324 ; frontend:front|packetfifo:hkfifo|start                                                                                             ; frontend:front|packetfifo:hkfifo|search                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.537      ; 1.076      ;
; 0.354 ; frontend:front|spi_slave:arm|rx_d_p[7]                                                                                             ; frontend:front|spi_slave:arm|rx_data[7]                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.541      ; 1.110      ;
; 0.361 ; frontend:front|spi_slave:arm|rx_d_p[14]                                                                                            ; frontend:front|spi_slave:arm|rx_data[14]                                                                                           ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.543      ; 1.119      ;
; 0.364 ; frontend:front|error_reg:master_errc|stat[4]                                                                                       ; frontend:front|error_reg:master_errc|stat[4]                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.364 ; frontend:front|packetfifo:hkfifo|search                                                                                            ; frontend:front|packetfifo:hkfifo|search                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 0.669      ;
; 0.381 ; frontend:front|spi_slave:arm|rx_d_p[15]                                                                                            ; frontend:front|spi_slave:arm|rx_data[15]                                                                                           ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.541      ; 1.137      ;
; 0.381 ; frontend:front|spi_slave:arm|rx_d_p[12]                                                                                            ; frontend:front|spi_slave:arm|rx_data[12]                                                                                           ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.543      ; 1.139      ;
; 0.382 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|full_dff         ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|full_dff         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; message:msg|t_shift[1]                                                                                                             ; message:msg|t_shift[1]                                                                                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; message:msg|t_shift[0]                                                                                                             ; message:msg|t_shift[0]                                                                                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; message:msg|t_shift[3]                                                                                                             ; message:msg|t_shift[3]                                                                                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; message:msg|crc_byte:crc_rx|bitcount[2]                                                                                            ; message:msg|crc_byte:crc_rx|bitcount[2]                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; message:msg|crc_byte:crc_rx|bitcount[1]                                                                                            ; message:msg|crc_byte:crc_rx|bitcount[1]                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[2]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[2]         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; frontend:front|error_reg:master_errc|stat[12]                                                                                      ; frontend:front|error_reg:master_errc|stat[12]                                                                                      ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; frontend:front|error_reg:master_errc|stat[13]                                                                                      ; frontend:front|error_reg:master_errc|stat[13]                                                                                      ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|full_dff         ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|full_dff         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]  ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[1]  ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[1]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[3]  ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[3]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[9]  ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[9]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|usedw_is_0_dff   ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|usedw_is_0_dff   ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; message:msg|uart:uart|uart_rx:rx1|attn                                                                                             ; message:msg|uart:uart|uart_rx:rx1|attn                                                                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; message:msg|uart:uart|uart_rx:rx2|attn                                                                                             ; message:msg|uart:uart|uart_rx:rx2|attn                                                                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; frontend:front|error_reg:master_errc|stat[11]                                                                                      ; frontend:front|error_reg:master_errc|stat[11]                                                                                      ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; message:msg|uart:uart|uart_rx:rx2|brk                                                                                              ; message:msg|uart:uart|uart_rx:rx2|brk                                                                                              ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; message:msg|uart:uart|uart_rx:rx1|busy                                                                                             ; message:msg|uart:uart|uart_rx:rx1|busy                                                                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; message:msg|uart:uart|uart_rx:rx1|clk1[1]                                                                                          ; message:msg|uart:uart|uart_rx:rx1|clk1[1]                                                                                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; message:msg|uart:uart|uart_rx:rx1|clk1[3]                                                                                          ; message:msg|uart:uart|uart_rx:rx1|clk1[3]                                                                                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; message:msg|uart:uart|uart_rx:rx1|clk1[2]                                                                                          ; message:msg|uart:uart|uart_rx:rx1|clk1[2]                                                                                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; message:msg|uart:uart|uart_rx:rx2|clk1[3]                                                                                          ; message:msg|uart:uart|uart_rx:rx2|clk1[3]                                                                                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; message:msg|uart:uart|uart_rx:rx2|clk1[2]                                                                                          ; message:msg|uart:uart|uart_rx:rx2|clk1[2]                                                                                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; message:msg|uart:uart|uart_rx:rx2|clk1[1]                                                                                          ; message:msg|uart:uart|uart_rx:rx2|clk1[1]                                                                                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; message:msg|uart:uart|baudgen:bgen|clk16div[3]                                                                                     ; message:msg|uart:uart|baudgen:bgen|clk16div[3]                                                                                     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; message:msg|uart:uart|baudgen:bgen|clk16div[2]                                                                                     ; message:msg|uart:uart|baudgen:bgen|clk16div[2]                                                                                     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; frontend:front|error_reg:master_errc|stat[0]                                                                                       ; frontend:front|error_reg:master_errc|stat[0]                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.382 ; frontend:front|error_reg:master_errc|stat[1]                                                                                       ; frontend:front|error_reg:master_errc|stat[1]                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.383 ; message:msg|uart:uart|uart_tx:tx|busy                                                                                              ; message:msg|uart:uart|uart_tx:tx|busy                                                                                              ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|uart:uart|uart_tx:tx|bc[1]                                                                                             ; message:msg|uart:uart|uart_tx:tx|bc[1]                                                                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|uart:uart|uart_tx:tx|bc[0]                                                                                             ; message:msg|uart:uart|uart_tx:tx|bc[0]                                                                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|uart:uart|uart_tx:tx|bc[3]                                                                                             ; message:msg|uart:uart|uart_tx:tx|bc[3]                                                                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|uart:uart|uart_tx:tx|bc[2]                                                                                             ; message:msg|uart:uart|uart_tx:tx|bc[2]                                                                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|spi_slave:arm|tx_avail                                                                                              ; frontend:front|spi_slave:arm|tx_avail                                                                                              ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]  ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[1]  ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[1]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[2]  ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[2]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[4]  ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[4]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[5]  ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[5]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[7]  ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[7]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[9]  ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[9]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[10] ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[10] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[7]                                                                   ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[7]                                                                   ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|cntl_reg:master_conf|stat[15]                                                                                       ; frontend:front|cntl_reg:master_conf|stat[15]                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[1]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[1]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[2]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[2]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[3]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[3]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[4]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[4]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[5]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[5]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[6]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[6]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[7]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[7]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[8]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[8]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[9]  ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[9]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[10] ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[10] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|t_phase[1]                                                                                                             ; message:msg|t_phase[1]                                                                                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|t_phase[0]                                                                                                             ; message:msg|t_phase[0]                                                                                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|crc_byte:crc_tx|busy                                                                                                   ; message:msg|crc_byte:crc_tx|busy                                                                                                   ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|full_dff                ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|full_dff                ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|cntl_reg:master_conf|stat[0]                                                                                        ; frontend:front|cntl_reg:master_conf|stat[0]                                                                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|dffe_af                               ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|dffe_af                               ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|cntl_reg:master_conf|stat[5]                                                                                        ; frontend:front|cntl_reg:master_conf|stat[5]                                                                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|cntl_reg:master_conf|stat[7]                                                                                        ; frontend:front|cntl_reg:master_conf|stat[7]                                                                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|crc_byte:crc_tx|bitcount[1]                                                                                            ; message:msg|crc_byte:crc_tx|bitcount[1]                                                                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|usedw_is_0_dff          ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|usedw_is_0_dff          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[0]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[0]         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[1]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[1]         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[3]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[3]         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[4]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[4]         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[5]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[5]         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[6]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[6]         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[7]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[7]         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[8]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[8]         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[9]         ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[9]         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|cntl_reg:master_conf|stat[9]                                                                                        ; frontend:front|cntl_reg:master_conf|stat[9]                                                                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; push_msg_cnt[2]                                                                                                                    ; push_msg_cnt[2]                                                                                                                    ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]  ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[1]  ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[1]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[2]  ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[2]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[3]  ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[3]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.383 ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[4]  ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[4]  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'spi_sck'                                                                                                                                                    ;
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                           ; To Node                                             ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.386 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[1]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.669      ;
; 0.386 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|frame[2]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.669      ;
; 0.401 ; frontend:front|spi_slave:arm|param                  ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.684      ;
; 0.401 ; frontend:front|spi_slave:arm|spi_timeout:tout|sclk2 ; frontend:front|spi_slave:arm|spi_timeout:tout|sclk2 ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.684      ;
; 0.462 ; frontend:front|spi_slave:arm|param                  ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.745      ;
; 0.463 ; frontend:front|spi_slave:arm|param                  ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.746      ;
; 0.473 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.756      ;
; 0.473 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[1]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.756      ;
; 0.474 ; frontend:front|spi_slave:arm|rx_sr[2]               ; frontend:front|spi_slave:arm|rx_sr[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.757      ;
; 0.474 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[2]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.757      ;
; 0.476 ; frontend:front|spi_slave:arm|rx_sr[5]               ; frontend:front|spi_slave:arm|rx_sr[6]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.759      ;
; 0.477 ; frontend:front|spi_slave:arm|rx_sr[7]               ; frontend:front|spi_slave:arm|rx_sr[8]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.760      ;
; 0.477 ; frontend:front|spi_slave:arm|rx_sr[4]               ; frontend:front|spi_slave:arm|rx_sr[5]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.760      ;
; 0.482 ; frontend:front|spi_slave:arm|rx_sr[12]              ; frontend:front|spi_slave:arm|rx_sr[13]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.765      ;
; 0.483 ; frontend:front|spi_slave:arm|rx_sr[8]               ; frontend:front|spi_slave:arm|rx_sr[9]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.766      ;
; 0.486 ; frontend:front|spi_slave:arm|rx_sr[1]               ; frontend:front|spi_slave:arm|rx_sr[2]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.769      ;
; 0.587 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.870      ;
; 0.614 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.897      ;
; 0.615 ; frontend:front|spi_slave:arm|rx_sr[9]               ; frontend:front|spi_slave:arm|rx_sr[10]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.898      ;
; 0.629 ; frontend:front|spi_slave:arm|tx_sr[11]              ; frontend:front|spi_slave:arm|tx_sr[12]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.912      ;
; 0.629 ; frontend:front|spi_slave:arm|tx_sr[6]               ; frontend:front|spi_slave:arm|tx_sr[7]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.069      ; 0.913      ;
; 0.629 ; frontend:front|spi_slave:arm|tx_sr[4]               ; frontend:front|spi_slave:arm|tx_sr[5]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.069      ; 0.913      ;
; 0.630 ; frontend:front|spi_slave:arm|tx_sr[5]               ; frontend:front|spi_slave:arm|tx_sr[6]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.069      ; 0.914      ;
; 0.630 ; frontend:front|spi_slave:arm|tx_sr[3]               ; frontend:front|spi_slave:arm|tx_sr[4]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.069      ; 0.914      ;
; 0.630 ; frontend:front|spi_slave:arm|tx_sr[2]               ; frontend:front|spi_slave:arm|tx_sr[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.069      ; 0.914      ;
; 0.631 ; frontend:front|spi_slave:arm|tx_sr[13]              ; frontend:front|spi_slave:arm|tx_sr[14]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.914      ;
; 0.631 ; frontend:front|spi_slave:arm|tx_sr[9]               ; frontend:front|spi_slave:arm|tx_sr[10]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.914      ;
; 0.632 ; frontend:front|spi_slave:arm|tx_sr[10]              ; frontend:front|spi_slave:arm|tx_sr[11]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.915      ;
; 0.632 ; frontend:front|spi_slave:arm|tx_sr[8]               ; frontend:front|spi_slave:arm|tx_sr[9]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.915      ;
; 0.641 ; frontend:front|spi_slave:arm|rx_sr[14]              ; frontend:front|spi_slave:arm|rx_sr[15]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.067      ; 0.923      ;
; 0.651 ; frontend:front|spi_slave:arm|rx_sr[10]              ; frontend:front|spi_slave:arm|rx_sr[11]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.934      ;
; 0.653 ; frontend:front|spi_slave:arm|rx_sr[6]               ; frontend:front|spi_slave:arm|rx_sr[7]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.936      ;
; 0.659 ; frontend:front|spi_slave:arm|rx_sr[13]              ; frontend:front|spi_slave:arm|rx_sr[14]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.942      ;
; 0.698 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_fetch               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 0.981      ;
; 0.726 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 1.009      ;
; 0.731 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 1.014      ;
; 0.803 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 1.086      ;
; 0.803 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 1.086      ;
; 0.814 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 1.097      ;
; 0.816 ; frontend:front|spi_slave:arm|rx_sr[0]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 0.000        ; 0.072      ; 1.103      ;
; 0.821 ; frontend:front|spi_slave:arm|tx_sr[12]              ; frontend:front|spi_slave:arm|tx_sr[13]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 1.104      ;
; 0.829 ; frontend:front|spi_slave:arm|rx_sr[0]               ; frontend:front|spi_slave:arm|rx_sr[1]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.071      ; 1.115      ;
; 0.833 ; frontend:front|spi_slave:arm|rx_sr[11]              ; frontend:front|spi_slave:arm|rx_sr[12]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 1.116      ;
; 0.853 ; frontend:front|spi_slave:arm|tx_sr[1]               ; frontend:front|spi_slave:arm|tx_sr[2]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.069      ; 1.137      ;
; 0.859 ; frontend:front|spi_slave:arm|tx_sr[0]               ; frontend:front|spi_slave:arm|tx_sr[1]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 1.142      ;
; 0.869 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 1.152      ;
; 0.902 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[2]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 1.185      ;
; 0.930 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 1.213      ;
; 0.945 ; frontend:front|spi_slave:arm|rx_sr[0]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.072      ; 1.232      ;
; 0.978 ; frontend:front|spi_slave:arm|rx_sr[3]               ; frontend:front|spi_slave:arm|rx_sr[4]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.063      ; 1.256      ;
; 1.077 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 1.360      ;
; 1.120 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 1.403      ;
; 1.155 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 1.438      ;
; 1.291 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 1.574      ;
; 1.346 ; frontend:front|spi_slave:arm|tx_sr[7]               ; frontend:front|spi_slave:arm|tx_sr[8]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.062      ; 1.623      ;
; 1.360 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 1.643      ;
; 1.363 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 1.646      ;
; 1.416 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.071      ; 1.702      ;
; 1.424 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[7]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.071      ; 1.710      ;
; 1.424 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[6]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.071      ; 1.710      ;
; 1.424 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[5]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.071      ; 1.710      ;
; 1.424 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[4]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.071      ; 1.710      ;
; 1.424 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.071      ; 1.710      ;
; 1.424 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[2]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.071      ; 1.710      ;
; 1.424 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[1]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.071      ; 1.710      ;
; 1.449 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[14]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.064      ; 1.728      ;
; 1.449 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[13]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.064      ; 1.728      ;
; 1.449 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[12]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.064      ; 1.728      ;
; 1.449 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[11]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.064      ; 1.728      ;
; 1.449 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[10]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.064      ; 1.728      ;
; 1.449 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[9]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.064      ; 1.728      ;
; 1.449 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[8]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.064      ; 1.728      ;
; 1.739 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 2.022      ;
; 1.739 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 2.022      ;
; 2.043 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 2.326      ;
; 2.043 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 2.326      ;
; 2.109 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 2.392      ;
; 2.109 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 2.392      ;
; 2.120 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 2.403      ;
; 2.120 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.068      ; 2.403      ;
; 2.573 ; frontend:front|spi_slave:arm|tx_sr[14]              ; frontend:front|spi_slave:arm|miso                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.018      ; 2.723      ;
; 3.040 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|miso                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.014      ; 3.186      ;
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'pll0|altpll_component|auto_generated|pll1|clk[1]'                                                                               ;
+--------+--------------+----------------+------------------+--------------------------------------------------+------------+------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                            ; Clock Edge ; Target                                         ;
+--------+--------------+----------------+------------------+--------------------------------------------------+------------+------------------------------------------------+
; 10.058 ; 10.274       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:hkfifo|rd[0]         ;
; 10.058 ; 10.274       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:hkfifo|rd[13]        ;
; 10.058 ; 10.274       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:hkfifo|rd[14]        ;
; 10.058 ; 10.274       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:hkfifo|rd[6]         ;
; 10.058 ; 10.274       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:hkfifo|search        ;
; 10.059 ; 10.275       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[16]  ;
; 10.059 ; 10.275       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[17]  ;
; 10.059 ; 10.275       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[18]  ;
; 10.059 ; 10.275       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[19]  ;
; 10.059 ; 10.275       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[21]  ;
; 10.059 ; 10.275       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[22]  ;
; 10.059 ; 10.275       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[23]  ;
; 10.059 ; 10.275       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[29]  ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[3].c|count[0]   ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[3].c|count[10]  ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[3].c|count[11]  ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[3].c|count[12]  ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[3].c|count[1]   ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[3].c|count[2]   ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[3].c|count[3]   ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[3].c|count[4]   ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[3].c|count[5]   ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[3].c|count[6]   ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[3].c|count[7]   ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[3].c|count[8]   ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[3].c|count[9]   ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|count[17] ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|count[20] ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|count[21] ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|count[23] ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|count[28] ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|count[29] ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|count[30] ;
; 10.060 ; 10.276       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|count[31] ;
; 10.061 ; 10.277       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[16]  ;
; 10.061 ; 10.277       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[17]  ;
; 10.061 ; 10.277       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[18]  ;
; 10.061 ; 10.277       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[19]  ;
; 10.061 ; 10.277       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[21]  ;
; 10.061 ; 10.277       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[22]  ;
; 10.061 ; 10.277       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[23]  ;
; 10.061 ; 10.277       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|count[29]  ;
; 10.061 ; 10.277       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|latch[17] ;
; 10.061 ; 10.277       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|latch[20] ;
; 10.061 ; 10.277       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|latch[28] ;
; 10.061 ; 10.277       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|latch[29] ;
; 10.061 ; 10.277       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|latch[30] ;
; 10.061 ; 10.277       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|cntr_reg:master_clock|latch[31] ;
; 10.061 ; 10.277       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|conf_reg:hkhdrvreg|stat[3]      ;
; 10.061 ; 10.277       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|conf_reg:hkhdrvreg|stat[5]      ;
; 10.061 ; 10.277       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|conf_reg:hkhdrvreg|stat[7]      ;
; 10.062 ; 10.278       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[22]  ;
; 10.062 ; 10.278       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[23]  ;
; 10.062 ; 10.278       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[27]  ;
; 10.062 ; 10.278       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[28]  ;
; 10.062 ; 10.278       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[29]  ;
; 10.062 ; 10.278       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[5].c|latch[17]  ;
; 10.062 ; 10.278       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[5].c|latch[18]  ;
; 10.062 ; 10.278       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[5].c|latch[19]  ;
; 10.062 ; 10.278       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[5].c|latch[22]  ;
; 10.062 ; 10.278       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[5].c|latch[26]  ;
; 10.062 ; 10.278       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[5].c|latch[28]  ;
; 10.062 ; 10.278       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[5].c|latch[29]  ;
; 10.062 ; 10.278       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[5].c|latch[30]  ;
; 10.062 ; 10.278       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; message:msg|timeout_ctr[15]                    ;
; 10.062 ; 10.278       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; message:msg|timeout_ctr[16]                    ;
; 10.062 ; 10.278       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; message:msg|timeout_ctr[17]                    ;
; 10.063 ; 10.279       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|wa[0]             ;
; 10.063 ; 10.279       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|wa[3]             ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[20]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[24]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[25]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[26]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[27]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[28]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[30]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[1].c|latch[31]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[16]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[17]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[18]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[22]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[28]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[29]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[30]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[18]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[21]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[22]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[24]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[25]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[26]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[29]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[30]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[31]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|latch[16]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|latch[17]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|latch[19]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|latch[20]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|latch[23]  ;
; 10.064 ; 10.280       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|latch[28]  ;
; 10.065 ; 10.281       ; 0.216          ; High Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; cntr_array:cntrs|cntr_reg:cntr[6].c|count[0]   ;
+--------+--------------+----------------+------------------+--------------------------------------------------+------------+------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'spi_sck'                                                                                    ;
+--------+--------------+----------------+------------------+---------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+---------+------------+-----------------------------------------------------+
; 16.406 ; 16.590       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[1]               ;
; 16.406 ; 16.590       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[2]               ;
; 16.406 ; 16.590       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[3]               ;
; 16.407 ; 16.591       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|addr                   ;
; 16.407 ; 16.591       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[0]               ;
; 16.407 ; 16.591       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[1]               ;
; 16.407 ; 16.591       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[2]               ;
; 16.407 ; 16.591       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[3]               ;
; 16.407 ; 16.591       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|last                   ;
; 16.407 ; 16.591       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|param                  ;
; 16.407 ; 16.591       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|spi_timeout:tout|sclk2 ;
; 16.407 ; 16.591       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_fetch               ;
; 16.407 ; 16.591       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[0]               ;
; 16.407 ; 16.591       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[1]               ;
; 16.407 ; 16.591       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[2]               ;
; 16.407 ; 16.591       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[3]               ;
; 16.407 ; 16.591       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[4]               ;
; 16.407 ; 16.591       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[5]               ;
; 16.407 ; 16.591       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[6]               ;
; 16.407 ; 16.591       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[7]               ;
; 16.407 ; 16.591       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|verylast               ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[0]               ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[10]              ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[11]              ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[12]              ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[13]              ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[14]              ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[15]              ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[4]               ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[5]               ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[6]               ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[7]               ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[8]               ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[9]               ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[10]              ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[11]              ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[12]              ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[13]              ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[14]              ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[8]               ;
; 16.408 ; 16.592       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[9]               ;
; 16.498 ; 16.653       ; 0.155          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|miso                   ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[0]               ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[10]              ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[11]              ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[12]              ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[13]              ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[14]              ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[15]              ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[4]               ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[5]               ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[6]               ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[7]               ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[8]               ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[9]               ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[10]              ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[11]              ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[12]              ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[13]              ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[14]              ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[8]               ;
; 16.520 ; 16.736       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[9]               ;
; 16.521 ; 16.737       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|addr                   ;
; 16.521 ; 16.737       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[0]               ;
; 16.521 ; 16.737       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[1]               ;
; 16.521 ; 16.737       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[2]               ;
; 16.521 ; 16.737       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[3]               ;
; 16.521 ; 16.737       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|last                   ;
; 16.521 ; 16.737       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|param                  ;
; 16.521 ; 16.737       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[1]               ;
; 16.521 ; 16.737       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[2]               ;
; 16.521 ; 16.737       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[3]               ;
; 16.521 ; 16.737       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|spi_timeout:tout|sclk2 ;
; 16.521 ; 16.737       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_fetch               ;
; 16.521 ; 16.737       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[0]               ;
; 16.521 ; 16.737       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|verylast               ;
; 16.522 ; 16.738       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[1]               ;
; 16.522 ; 16.738       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[2]               ;
; 16.522 ; 16.738       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[3]               ;
; 16.522 ; 16.738       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[4]               ;
; 16.522 ; 16.738       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[5]               ;
; 16.522 ; 16.738       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[6]               ;
; 16.522 ; 16.738       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[7]               ;
; 16.528 ; 16.678       ; 0.150          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|miso                   ;
; 16.630 ; 16.630       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|rx_sr[1]|clk                              ;
; 16.630 ; 16.630       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|rx_sr[2]|clk                              ;
; 16.630 ; 16.630       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|rx_sr[3]|clk                              ;
; 16.631 ; 16.631       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|addr|clk                                  ;
; 16.631 ; 16.631       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|frame[0]|clk                              ;
; 16.631 ; 16.631       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|frame[1]|clk                              ;
; 16.631 ; 16.631       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|frame[2]|clk                              ;
; 16.631 ; 16.631       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|frame[3]|clk                              ;
; 16.631 ; 16.631       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|last|clk                                  ;
; 16.631 ; 16.631       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|param|clk                                 ;
; 16.631 ; 16.631       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|tout|sclk2|clk                            ;
; 16.631 ; 16.631       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|tx_fetch|clk                              ;
; 16.631 ; 16.631       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|tx_sr[0]|clk                              ;
; 16.631 ; 16.631       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|tx_sr[1]|clk                              ;
; 16.631 ; 16.631       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|tx_sr[2]|clk                              ;
; 16.631 ; 16.631       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|tx_sr[3]|clk                              ;
+--------+--------------+----------------+------------------+---------+------------+-----------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'clk_12'                                                                                           ;
+--------+--------------+----------------+------------------+--------+------------+------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target                                                     ;
+--------+--------------+----------------+------------------+--------+------------+------------------------------------------------------------+
; 41.567 ; 41.567       ; 0.000          ; High Pulse Width ; clk_12 ; Rise       ; pll0|altpll_component|auto_generated|pll1|inclk[0]         ;
; 41.586 ; 41.586       ; 0.000          ; High Pulse Width ; clk_12 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1]           ;
; 41.586 ; 41.586       ; 0.000          ; High Pulse Width ; clk_12 ; Rise       ; pll0|altpll_component|auto_generated|pll1|observablevcoout ;
; 41.592 ; 41.592       ; 0.000          ; High Pulse Width ; clk_12 ; Rise       ; clk_12~input|o                                             ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clk_12 ; Rise       ; clk_12~input|i                                             ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clk_12 ; Rise       ; clk_12~input|i                                             ;
; 41.739 ; 41.739       ; 0.000          ; Low Pulse Width  ; clk_12 ; Rise       ; clk_12~input|o                                             ;
; 41.746 ; 41.746       ; 0.000          ; Low Pulse Width  ; clk_12 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1]           ;
; 41.746 ; 41.746       ; 0.000          ; Low Pulse Width  ; clk_12 ; Rise       ; pll0|altpll_component|auto_generated|pll1|observablevcoout ;
; 41.763 ; 41.763       ; 0.000          ; Low Pulse Width  ; clk_12 ; Rise       ; pll0|altpll_component|auto_generated|pll1|inclk[0]         ;
; 80.208 ; 83.333       ; 3.125          ; Port Rate        ; clk_12 ; Rise       ; clk_12                                                     ;
+--------+--------------+----------------+------------------+--------+------------+------------------------------------------------------------+


+-----------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'clk_T1'                                ;
+--------+--------------+----------------+-----------+--------+------------+--------+
; Slack  ; Actual Width ; Required Width ; Type      ; Clock  ; Clock Edge ; Target ;
+--------+--------------+----------------+-----------+--------+------------+--------+
; 63.542 ; 66.667       ; 3.125          ; Port Rate ; clk_T1 ; Rise       ; clk_T1 ;
+--------+--------------+----------------+-----------+--------+------------+--------+


+----------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                              ;
+-----------+------------+--------+--------+------------+--------------------------------------------------+
; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                  ;
+-----------+------------+--------+--------+------------+--------------------------------------------------+
; Rx[*]     ; clk_12     ; 0.059  ; 0.148  ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Rx[2]    ; clk_12     ; -0.210 ; -0.045 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Rx[3]    ; clk_12     ; 0.059  ; 0.148  ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; spi_mosi  ; spi_sck    ; 0.330  ; 0.490  ; Fall       ; spi_sck                                          ;
+-----------+------------+--------+--------+------------+--------------------------------------------------+


+---------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                              ;
+-----------+------------+-------+--------+------------+--------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall   ; Clock Edge ; Clock Reference                                  ;
+-----------+------------+-------+--------+------------+--------------------------------------------------+
; Rx[*]     ; clk_12     ; 0.936 ; 0.776  ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Rx[2]    ; clk_12     ; 0.936 ; 0.776  ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Rx[3]    ; clk_12     ; 0.679 ; 0.592  ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; spi_mosi  ; spi_sck    ; 0.090 ; -0.054 ; Fall       ; spi_sck                                          ;
+-----------+------------+-------+--------+------------+--------------------------------------------------+


+------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                      ;
+-------------+------------+--------+--------+------------+--------------------------------------------------+
; Data Port   ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                  ;
+-------------+------------+--------+--------+------------+--------------------------------------------------+
; Tx[*]       ; clk_12     ; 14.995 ; 14.809 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Tx[1]      ; clk_12     ; 13.181 ; 12.784 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Tx[2]      ; clk_12     ; 14.995 ; 14.809 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; attn        ; clk_12     ; 14.349 ; 13.633 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; spi_miso    ; spi_sck    ; 7.973  ; 7.957  ; Fall       ; spi_sck                                          ;
; spi_miso(n) ; spi_sck    ; 7.957  ; 7.973  ; Fall       ; spi_sck                                          ;
+-------------+------------+--------+--------+------------+--------------------------------------------------+


+------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                              ;
+-------------+------------+--------+--------+------------+--------------------------------------------------+
; Data Port   ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                  ;
+-------------+------------+--------+--------+------------+--------------------------------------------------+
; Tx[*]       ; clk_12     ; 10.813 ; 10.496 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Tx[1]      ; clk_12     ; 10.813 ; 10.496 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Tx[2]      ; clk_12     ; 12.351 ; 12.148 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; attn        ; clk_12     ; 13.076 ; 12.412 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; spi_miso    ; spi_sck    ; 7.864  ; 7.849  ; Fall       ; spi_sck                                          ;
; spi_miso(n) ; spi_sck    ; 7.849  ; 7.864  ; Fall       ; spi_sck                                          ;
+-------------+------------+--------+--------+------------+--------------------------------------------------+


+------------------------------------------------------+
; Propagation Delay                                    ;
+------------+-------------+--------+----+----+--------+
; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
+------------+-------------+--------+----+----+--------+
; Rx[2]      ; Tx[1]       ; 9.458  ;    ;    ; 9.258  ;
; Rx[3]      ; Tx[2]       ; 11.509 ;    ;    ; 11.301 ;
+------------+-------------+--------+----+----+--------+


+------------------------------------------------------+
; Minimum Propagation Delay                            ;
+------------+-------------+--------+----+----+--------+
; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
+------------+-------------+--------+----+----+--------+
; Rx[2]      ; Tx[1]       ; 9.177  ;    ;    ; 8.983  ;
; Rx[3]      ; Tx[2]       ; 11.230 ;    ;    ; 11.033 ;
+------------+-------------+--------+----+----+--------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                        ;
+--------------------------------------------------+--------+---------------+
; Clock                                            ; Slack  ; End Point TNS ;
+--------------------------------------------------+--------+---------------+
; pll0|altpll_component|auto_generated|pll1|clk[1] ; 9.254  ; 0.000         ;
; spi_sck                                          ; 31.481 ; 0.000         ;
+--------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                        ;
+--------------------------------------------------+-------+---------------+
; Clock                                            ; Slack ; End Point TNS ;
+--------------------------------------------------+-------+---------------+
; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.035 ; 0.000         ;
; spi_sck                                          ; 0.166 ; 0.000         ;
+--------------------------------------------------+-------+---------------+


-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+---------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                          ;
+--------------------------------------------------+--------+---------------+
; Clock                                            ; Slack  ; End Point TNS ;
+--------------------------------------------------+--------+---------------+
; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.165 ; 0.000         ;
; spi_sck                                          ; 16.454 ; 0.000         ;
; clk_12                                           ; 41.622 ; 0.000         ;
; clk_T1                                           ; 64.384 ; 0.000         ;
+--------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'pll0|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                   ;
+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                             ; To Node                                                          ; Launch Clock                                     ; Latch Clock                                      ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+------------+------------+
; 9.254  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_addr                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.267     ; 0.883      ;
; 9.255  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_exec                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.267     ; 0.882      ;
; 9.267  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[11]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.082     ; 1.055      ;
; 9.267  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[10]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.082     ; 1.055      ;
; 9.267  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[3]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.082     ; 1.055      ;
; 9.283  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_addr                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.267     ; 0.854      ;
; 9.284  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_exec                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.267     ; 0.853      ;
; 9.296  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[11]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.082     ; 1.026      ;
; 9.296  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[10]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.082     ; 1.026      ;
; 9.296  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[3]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.082     ; 1.026      ;
; 9.382  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[15]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.956      ;
; 9.382  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[14]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.956      ;
; 9.382  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[13]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.956      ;
; 9.382  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[12]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.956      ;
; 9.382  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[8]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.956      ;
; 9.382  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[2]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.956      ;
; 9.382  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[9]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.956      ;
; 9.382  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[1]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.956      ;
; 9.382  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[0]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.956      ;
; 9.382  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[4]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.956      ;
; 9.382  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[5]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.956      ;
; 9.382  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[7]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.956      ;
; 9.382  ; frontend:front|spi_slave:arm|frame_done_n[1]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[6]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.956      ;
; 9.411  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[15]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.927      ;
; 9.411  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[14]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.927      ;
; 9.411  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[13]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.927      ;
; 9.411  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[12]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.927      ;
; 9.411  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[8]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.927      ;
; 9.411  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[2]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.927      ;
; 9.411  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[9]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.927      ;
; 9.411  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[1]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.927      ;
; 9.411  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[0]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.927      ;
; 9.411  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[4]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.927      ;
; 9.411  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[5]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.927      ;
; 9.411  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[7]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.927      ;
; 9.411  ; frontend:front|spi_slave:arm|frame_done_n[0]                                                                                                          ; frontend:front|spi_slave:arm|rx_data[6]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.927      ;
; 9.432  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[6] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.056     ; 0.916      ;
; 9.432  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[5] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.056     ; 0.916      ;
; 9.432  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[4] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.056     ; 0.916      ;
; 9.432  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[3] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.056     ; 0.916      ;
; 9.432  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[2] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.056     ; 0.916      ;
; 9.432  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.056     ; 0.916      ;
; 9.432  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[0] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.056     ; 0.916      ;
; 9.507  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[1]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[7] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.056     ; 0.841      ;
; 9.518  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[6] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.056     ; 0.830      ;
; 9.518  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[5] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.056     ; 0.830      ;
; 9.518  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[4] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.056     ; 0.830      ;
; 9.518  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[3] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.056     ; 0.830      ;
; 9.518  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[2] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.056     ; 0.830      ;
; 9.518  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.056     ; 0.830      ;
; 9.518  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[0] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.056     ; 0.830      ;
; 9.616  ; frontend:front|spi_slave:arm|rx_d_n[13]                                                                                                               ; frontend:front|spi_slave:arm|rx_data[13]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.066     ; 0.722      ;
; 9.629  ; frontend:front|spi_slave:arm|rx_d_n[9]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[9]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.137      ; 0.912      ;
; 9.675  ; frontend:front|spi_slave:arm|spi_timeout:tout|sclkn[2]                                                                                                ; frontend:front|spi_slave:arm|spi_timeout:tout|timeout_counter[7] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.056     ; 0.673      ;
; 9.801  ; frontend:front|spi_slave:arm|rx_d_n[7]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[7]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.135      ; 0.738      ;
; 9.810  ; frontend:front|spi_slave:arm|rx_d_n[12]                                                                                                               ; frontend:front|spi_slave:arm|rx_data[12]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.137      ; 0.731      ;
; 9.903  ; frontend:front|spi_slave:arm|rx_d_n[4]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[4]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.135      ; 0.636      ;
; 9.919  ; frontend:front|spi_slave:arm|rx_d_n[1]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[1]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.146      ; 0.631      ;
; 9.927  ; frontend:front|spi_slave:arm|rx_d_n[0]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[0]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.135      ; 0.612      ;
; 9.928  ; frontend:front|spi_slave:arm|rx_d_n[8]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[8]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.143      ; 0.619      ;
; 9.929  ; frontend:front|spi_slave:arm|tx_fetch_nn                                                                                                              ; frontend:front|spi_slave:arm|tx_fetched                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.056     ; 0.419      ;
; 9.966  ; frontend:front|spi_slave:arm|rx_d_n[2]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[2]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.135      ; 0.573      ;
; 9.971  ; frontend:front|spi_slave:arm|tx_fetch_n                                                                                                               ; frontend:front|spi_slave:arm|tx_fetched                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; -0.056     ; 0.377      ;
; 9.987  ; frontend:front|spi_slave:arm|rx_d_n[14]                                                                                                               ; frontend:front|spi_slave:arm|rx_data[14]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.137      ; 0.554      ;
; 9.990  ; frontend:front|spi_slave:arm|rx_d_n[6]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[6]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.135      ; 0.549      ;
; 9.996  ; frontend:front|spi_slave:arm|rx_d_n[5]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[5]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.135      ; 0.543      ;
; 10.065 ; frontend:front|spi_slave:arm|rx_d_n[11]                                                                                                               ; frontend:front|spi_slave:arm|rx_data[11]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.126      ; 0.465      ;
; 10.074 ; frontend:front|spi_slave:arm|rx_d_n[3]                                                                                                                ; frontend:front|spi_slave:arm|rx_data[3]                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.126      ; 0.456      ;
; 10.080 ; frontend:front|spi_slave:arm|rx_d_n[15]                                                                                                               ; frontend:front|spi_slave:arm|rx_data[15]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.135      ; 0.459      ;
; 10.083 ; frontend:front|spi_slave:arm|rx_d_n[10]                                                                                                               ; frontend:front|spi_slave:arm|rx_data[10]                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 10.417       ; 0.127      ; 0.448      ;
; 18.281 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[8]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.363      ;
; 18.281 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[4]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.363      ;
; 18.281 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[6]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.363      ;
; 18.281 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[5]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.363      ;
; 18.281 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[7]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.363      ;
; 18.281 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[1]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.363      ;
; 18.281 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[0]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.363      ;
; 18.281 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[2]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.363      ;
; 18.281 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13] ; frontend:front|packetfifo:hkfifo|count[3]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.363      ;
; 18.325 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[8]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.179     ; 2.316      ;
; 18.325 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[4]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.179     ; 2.316      ;
; 18.325 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[6]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.179     ; 2.316      ;
; 18.325 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[5]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.179     ; 2.316      ;
; 18.325 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[7]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.179     ; 2.316      ;
; 18.325 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[1]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.179     ; 2.316      ;
; 18.325 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[0]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.179     ; 2.316      ;
; 18.325 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[2]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.179     ; 2.316      ;
; 18.325 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]  ; frontend:front|packetfifo:hkfifo|count[3]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.179     ; 2.316      ;
; 18.352 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[8]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.292      ;
; 18.352 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[4]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.292      ;
; 18.352 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[6]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.292      ;
; 18.352 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[5]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.292      ;
; 18.352 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[7]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.292      ;
; 18.352 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[1]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.292      ;
; 18.352 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[0]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.292      ;
; 18.352 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[2]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.292      ;
; 18.352 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15] ; frontend:front|packetfifo:hkfifo|count[3]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.292      ;
; 18.374 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[0]  ; frontend:front|packetfifo:hkfifo|count[8]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.270      ;
; 18.374 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[0]  ; frontend:front|packetfifo:hkfifo|count[4]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.270      ;
; 18.374 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[0]  ; frontend:front|packetfifo:hkfifo|count[6]                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 20.833       ; -0.176     ; 2.270      ;
+--------+-------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'spi_sck'                                                                                                                                                    ;
+--------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                           ; To Node                                             ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 31.481 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|miso                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.079     ; 1.713      ;
; 31.733 ; frontend:front|spi_slave:arm|tx_sr[14]              ; frontend:front|spi_slave:arm|miso                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.075     ; 1.465      ;
; 32.148 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 1.135      ;
; 32.148 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 1.135      ;
; 32.154 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 1.129      ;
; 32.154 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 1.129      ;
; 32.218 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 1.065      ;
; 32.218 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 1.065      ;
; 32.339 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.944      ;
; 32.339 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.944      ;
; 32.385 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.898      ;
; 32.391 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.892      ;
; 32.397 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[14]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.041     ; 0.882      ;
; 32.397 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[13]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.041     ; 0.882      ;
; 32.397 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[12]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.041     ; 0.882      ;
; 32.397 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[11]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.041     ; 0.882      ;
; 32.397 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[10]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.041     ; 0.882      ;
; 32.397 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[9]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.041     ; 0.882      ;
; 32.397 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[8]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.041     ; 0.882      ;
; 32.422 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[7]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.035     ; 0.863      ;
; 32.422 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[6]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.035     ; 0.863      ;
; 32.422 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[5]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.035     ; 0.863      ;
; 32.422 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[4]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.035     ; 0.863      ;
; 32.422 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.035     ; 0.863      ;
; 32.422 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[2]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.035     ; 0.863      ;
; 32.422 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[1]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.035     ; 0.863      ;
; 32.438 ; frontend:front|spi_slave:arm|tx_sr[7]               ; frontend:front|spi_slave:arm|tx_sr[8]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.044     ; 0.838      ;
; 32.454 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.035     ; 0.831      ;
; 32.455 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.828      ;
; 32.536 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.747      ;
; 32.545 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.738      ;
; 32.546 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.737      ;
; 32.623 ; frontend:front|spi_slave:arm|rx_sr[3]               ; frontend:front|spi_slave:arm|rx_sr[4]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.043     ; 0.654      ;
; 32.645 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.638      ;
; 32.669 ; frontend:front|spi_slave:arm|rx_sr[0]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.033     ; 0.618      ;
; 32.676 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[2]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.607      ;
; 32.695 ; frontend:front|spi_slave:arm|rx_sr[0]               ; frontend:front|spi_slave:arm|rx_sr[1]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.034     ; 0.591      ;
; 32.702 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.581      ;
; 32.706 ; frontend:front|spi_slave:arm|rx_sr[0]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 33.333       ; -0.033     ; 0.581      ;
; 32.708 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.575      ;
; 32.717 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.566      ;
; 32.721 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.562      ;
; 32.744 ; frontend:front|spi_slave:arm|tx_sr[1]               ; frontend:front|spi_slave:arm|tx_sr[2]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.538      ;
; 32.745 ; frontend:front|spi_slave:arm|tx_sr[0]               ; frontend:front|spi_slave:arm|tx_sr[1]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.537      ;
; 32.757 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_fetch               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.526      ;
; 32.759 ; frontend:front|spi_slave:arm|rx_sr[11]              ; frontend:front|spi_slave:arm|rx_sr[12]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.523      ;
; 32.768 ; frontend:front|spi_slave:arm|tx_sr[12]              ; frontend:front|spi_slave:arm|tx_sr[13]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.515      ;
; 32.768 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.515      ;
; 32.769 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.514      ;
; 32.809 ; frontend:front|spi_slave:arm|rx_sr[14]              ; frontend:front|spi_slave:arm|rx_sr[15]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.039     ; 0.472      ;
; 32.821 ; frontend:front|spi_slave:arm|rx_sr[9]               ; frontend:front|spi_slave:arm|rx_sr[10]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.461      ;
; 32.827 ; frontend:front|spi_slave:arm|rx_sr[13]              ; frontend:front|spi_slave:arm|rx_sr[14]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.455      ;
; 32.830 ; frontend:front|spi_slave:arm|rx_sr[6]               ; frontend:front|spi_slave:arm|rx_sr[7]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.452      ;
; 32.832 ; frontend:front|spi_slave:arm|rx_sr[10]              ; frontend:front|spi_slave:arm|rx_sr[11]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.450      ;
; 32.832 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.451      ;
; 32.842 ; frontend:front|spi_slave:arm|tx_sr[10]              ; frontend:front|spi_slave:arm|tx_sr[11]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.441      ;
; 32.842 ; frontend:front|spi_slave:arm|tx_sr[8]               ; frontend:front|spi_slave:arm|tx_sr[9]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.441      ;
; 32.842 ; frontend:front|spi_slave:arm|tx_sr[2]               ; frontend:front|spi_slave:arm|tx_sr[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.440      ;
; 32.843 ; frontend:front|spi_slave:arm|tx_sr[9]               ; frontend:front|spi_slave:arm|tx_sr[10]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.440      ;
; 32.843 ; frontend:front|spi_slave:arm|tx_sr[4]               ; frontend:front|spi_slave:arm|tx_sr[5]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.439      ;
; 32.843 ; frontend:front|spi_slave:arm|tx_sr[3]               ; frontend:front|spi_slave:arm|tx_sr[4]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.439      ;
; 32.843 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.440      ;
; 32.844 ; frontend:front|spi_slave:arm|tx_sr[6]               ; frontend:front|spi_slave:arm|tx_sr[7]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.438      ;
; 32.844 ; frontend:front|spi_slave:arm|tx_sr[5]               ; frontend:front|spi_slave:arm|tx_sr[6]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.438      ;
; 32.845 ; frontend:front|spi_slave:arm|tx_sr[13]              ; frontend:front|spi_slave:arm|tx_sr[14]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.438      ;
; 32.846 ; frontend:front|spi_slave:arm|tx_sr[11]              ; frontend:front|spi_slave:arm|tx_sr[12]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.437      ;
; 32.879 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[1]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.404      ;
; 32.879 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[2]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.404      ;
; 32.882 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.401      ;
; 32.888 ; frontend:front|spi_slave:arm|rx_sr[1]               ; frontend:front|spi_slave:arm|rx_sr[2]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.394      ;
; 32.893 ; frontend:front|spi_slave:arm|rx_sr[8]               ; frontend:front|spi_slave:arm|rx_sr[9]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.389      ;
; 32.894 ; frontend:front|spi_slave:arm|rx_sr[12]              ; frontend:front|spi_slave:arm|rx_sr[13]              ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.388      ;
; 32.895 ; frontend:front|spi_slave:arm|param                  ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.388      ;
; 32.896 ; frontend:front|spi_slave:arm|rx_sr[4]               ; frontend:front|spi_slave:arm|rx_sr[5]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.386      ;
; 32.896 ; frontend:front|spi_slave:arm|param                  ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.387      ;
; 32.897 ; frontend:front|spi_slave:arm|rx_sr[7]               ; frontend:front|spi_slave:arm|rx_sr[8]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.385      ;
; 32.898 ; frontend:front|spi_slave:arm|rx_sr[5]               ; frontend:front|spi_slave:arm|rx_sr[6]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.384      ;
; 32.899 ; frontend:front|spi_slave:arm|rx_sr[2]               ; frontend:front|spi_slave:arm|rx_sr[3]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.383      ;
; 32.923 ; frontend:front|spi_slave:arm|spi_timeout:tout|sclk2 ; frontend:front|spi_slave:arm|spi_timeout:tout|sclk2 ; spi_sck      ; spi_sck     ; 33.333       ; -0.038     ; 0.359      ;
; 32.924 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|frame[2]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.359      ;
; 32.924 ; frontend:front|spi_slave:arm|param                  ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.359      ;
; 32.924 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[1]               ; spi_sck      ; spi_sck     ; 33.333       ; -0.037     ; 0.359      ;
+--------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'pll0|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                ; To Node                                                                                                                                                                       ; Launch Clock                                     ; Latch Clock                                      ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+------------+------------+
; 0.035 ; frontend:front|spi_slave:arm|rx_d_p[9]                                                                                                                   ; frontend:front|spi_slave:arm|rx_data[9]                                                                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.238      ; 0.377      ;
; 0.038 ; frontend:front|spi_slave:arm|rx_d_p[13]                                                                                                                  ; frontend:front|spi_slave:arm|rx_data[13]                                                                                                                                      ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.238      ; 0.380      ;
; 0.040 ; frontend:front|spi_slave:arm|rx_d_p[0]                                                                                                                   ; frontend:front|spi_slave:arm|rx_data[0]                                                                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.237      ; 0.381      ;
; 0.052 ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[28]                                                                                                            ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[28]                                                                                                                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.229      ; 0.385      ;
; 0.102 ; frontend:front|spi_slave:arm|rx_d_p[4]                                                                                                                   ; frontend:front|spi_slave:arm|rx_data[4]                                                                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.237      ; 0.443      ;
; 0.104 ; cntr_array:cntrs|cntr_reg:cntr[2].c|latch[14]                                                                                                            ; cntr_array:cntrs|cntr_reg:cntr[2].c|count[14]                                                                                                                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.217      ; 0.425      ;
; 0.113 ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[23]                                                                                                            ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[23]                                                                                                                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.229      ; 0.446      ;
; 0.114 ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[29]                                                                                                            ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[29]                                                                                                                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.229      ; 0.447      ;
; 0.115 ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[27]                                                                                                            ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[27]                                                                                                                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.229      ; 0.448      ;
; 0.117 ; cntr_array:cntrs|cntr_reg:cntr[4].c|count[22]                                                                                                            ; cntr_array:cntrs|cntr_reg:cntr[4].c|latch[22]                                                                                                                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.229      ; 0.450      ;
; 0.137 ; frontend:front|spi_slave:arm|rx_d_p[14]                                                                                                                  ; frontend:front|spi_slave:arm|rx_data[14]                                                                                                                                      ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.238      ; 0.479      ;
; 0.137 ; message:msg|tx_data[3]                                                                                                                                   ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram|ram_block1a0~porta_datain_reg0             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.482      ;
; 0.142 ; frontend:front|spi_slave:arm|rx_d_p[15]                                                                                                                  ; frontend:front|spi_slave:arm|rx_data[15]                                                                                                                                      ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.237      ; 0.483      ;
; 0.146 ; frontend:front|packetfifo:hkfifo|start                                                                                                                   ; frontend:front|packetfifo:hkfifo|search                                                                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.232      ; 0.482      ;
; 0.153 ; frontend:front|spi_slave:arm|rx_d_p[12]                                                                                                                  ; frontend:front|spi_slave:arm|rx_data[12]                                                                                                                                      ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.238      ; 0.495      ;
; 0.154 ; frontend:front|spi_slave:arm|rx_d_p[11]                                                                                                                  ; frontend:front|spi_slave:arm|rx_data[11]                                                                                                                                      ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.482      ;
; 0.155 ; frontend:front|spi_slave:arm|rx_d_p[8]                                                                                                                   ; frontend:front|spi_slave:arm|rx_data[8]                                                                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.238      ; 0.497      ;
; 0.155 ; frontend:front|spi_slave:arm|rx_d_p[7]                                                                                                                   ; frontend:front|spi_slave:arm|rx_data[7]                                                                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.237      ; 0.496      ;
; 0.156 ; frontend:front|spi_slave:arm|rx_d_p[2]                                                                                                                   ; frontend:front|spi_slave:arm|rx_data[2]                                                                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.237      ; 0.497      ;
; 0.157 ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_2ab:wr_ptr|counter_reg_bit[5]     ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a1~porta_address_reg0     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.228      ; 0.509      ;
; 0.157 ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_2ab:wr_ptr|counter_reg_bit[6]     ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a1~porta_address_reg0     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.228      ; 0.509      ;
; 0.158 ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_2ab:wr_ptr|counter_reg_bit[6]     ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a8~porta_address_reg0     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.228      ; 0.510      ;
; 0.159 ; frontend:front|error_reg:master_errc|stat[4]                                                                                                             ; frontend:front|error_reg:master_errc|stat[4]                                                                                                                                  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.159 ; frontend:front|packetfifo:hkfifo|search                                                                                                                  ; frontend:front|packetfifo:hkfifo|search                                                                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.162 ; frontend:front|spi_slave:arm|rx_d_p[5]                                                                                                                   ; frontend:front|spi_slave:arm|rx_data[5]                                                                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.237      ; 0.503      ;
; 0.163 ; frontend:front|spi_slave:arm|rx_d_p[6]                                                                                                                   ; frontend:front|spi_slave:arm|rx_data[6]                                                                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.237      ; 0.504      ;
; 0.165 ; frontend:front|spi_slave:arm|rx_d_p[10]                                                                                                                  ; frontend:front|spi_slave:arm|rx_data[10]                                                                                                                                      ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.494      ;
; 0.166 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]                        ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[1]                        ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[1]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[2]                        ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[2]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[4]                        ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[4]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[5]                        ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[5]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[6]                        ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[6]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[7]                        ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[7]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[9]                        ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[9]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[10]                       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[10]                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|usedw_is_0_dff                                ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|usedw_is_0_dff                                                     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[0]                               ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[0]                                                    ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[3]                               ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[3]                                                    ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[7]                               ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[7]                                                    ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[8]                               ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[8]                                                    ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_2ab:wr_ptr|counter_reg_bit[2] ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a0~porta_address_reg0 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.215      ; 0.505      ;
; 0.166 ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]                        ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[3]                        ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[3]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|usedw_is_0_dff                         ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|usedw_is_0_dff                                              ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; message:msg|uart:uart|uart_rx:rx1|brk                                                                                                                    ; message:msg|uart:uart|uart_rx:rx1|brk                                                                                                                                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; message:msg|uart:uart|uart_rx:rx2|clk1[3]                                                                                                                ; message:msg|uart:uart|uart_rx:rx2|clk1[3]                                                                                                                                     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; message:msg|uart:uart|uart_rx:rx2|clk1[2]                                                                                                                ; message:msg|uart:uart|uart_rx:rx2|clk1[2]                                                                                                                                     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; message:msg|uart:uart|uart_rx:rx2|clk1[1]                                                                                                                ; message:msg|uart:uart|uart_rx:rx2|clk1[1]                                                                                                                                     ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.167 ; message:msg|uart:uart|uart_tx:tx|busy                                                                                                                    ; message:msg|uart:uart|uart_tx:tx|busy                                                                                                                                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|uart:uart|uart_tx:tx|bc[1]                                                                                                                   ; message:msg|uart:uart|uart_tx:tx|bc[1]                                                                                                                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|uart:uart|uart_tx:tx|bc[0]                                                                                                                   ; message:msg|uart:uart|uart_tx:tx|bc[0]                                                                                                                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|uart:uart|uart_tx:tx|bc[3]                                                                                                                   ; message:msg|uart:uart|uart_tx:tx|bc[3]                                                                                                                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|uart:uart|uart_tx:tx|bc[2]                                                                                                                   ; message:msg|uart:uart|uart_tx:tx|bc[2]                                                                                                                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|spi_slave:arm|tx_avail                                                                                                                    ; frontend:front|spi_slave:arm|tx_avail                                                                                                                                         ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]                        ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[0]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[1]                        ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[1]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[2]                        ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[2]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[3]                        ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[3]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[4]                        ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[4]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[5]                        ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[5]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[6]                        ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[6]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[7]                        ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[7]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[8]                        ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[8]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[9]                        ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[9]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[10]                       ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[10]                                            ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|error_reg:master_errc|stat[14]                                                                                                            ; frontend:front|error_reg:master_errc|stat[14]                                                                                                                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|cntl_reg:master_conf|stat[15]                                                                                                             ; frontend:front|cntl_reg:master_conf|stat[15]                                                                                                                                  ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|error_reg:master_errc|stat[15]                                                                                                            ; frontend:front|error_reg:master_errc|stat[15]                                                                                                                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|full_dff                               ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|full_dff                                                    ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[3]                        ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[3]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[8]                        ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|low_addressa[8]                                             ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|t_phase[1]                                                                                                                                   ; message:msg|t_phase[1]                                                                                                                                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|t_phase[0]                                                                                                                                   ; message:msg|t_phase[0]                                                                                                                                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|crc_byte:crc_tx|busy                                                                                                                         ; message:msg|crc_byte:crc_tx|busy                                                                                                                                              ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|full_dff                                      ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|full_dff                                                           ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|t_shift[1]                                                                                                                                   ; message:msg|t_shift[1]                                                                                                                                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|t_shift[0]                                                                                                                                   ; message:msg|t_shift[0]                                                                                                                                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|t_shift[3]                                                                                                                                   ; message:msg|t_shift[3]                                                                                                                                                        ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|cntl_reg:master_conf|stat[0]                                                                                                              ; frontend:front|cntl_reg:master_conf|stat[0]                                                                                                                                   ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|dffe_af                                                     ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|dffe_af                                                                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|cntl_reg:master_conf|stat[5]                                                                                                              ; frontend:front|cntl_reg:master_conf|stat[5]                                                                                                                                   ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|cntl_reg:master_conf|stat[7]                                                                                                              ; frontend:front|cntl_reg:master_conf|stat[7]                                                                                                                                   ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|cntl_reg:master_conf|stat[4]                                                                                                              ; frontend:front|cntl_reg:master_conf|stat[4]                                                                                                                                   ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|crc_byte:crc_tx|bitcount[1]                                                                                                                  ; message:msg|crc_byte:crc_tx|bitcount[1]                                                                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|cntl_reg:master_conf|stat[3]                                                                                                              ; frontend:front|cntl_reg:master_conf|stat[3]                                                                                                                                   ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|crc_byte:crc_rx|bitcount[2]                                                                                                                  ; message:msg|crc_byte:crc_rx|bitcount[2]                                                                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|crc_byte:crc_rx|bitcount[1]                                                                                                                  ; message:msg|crc_byte:crc_rx|bitcount[1]                                                                                                                                       ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[1]                               ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[1]                                                    ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[2]                               ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[2]                                                    ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[4]                               ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[4]                                                    ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[5]                               ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[5]                                                    ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[6]                               ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[6]                                                    ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[9]                               ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|low_addressa[9]                                                    ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|cntr_2ab:wr_ptr|counter_reg_bit[1]     ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a12~porta_address_reg0    ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.516      ;
; 0.167 ; frontend:front|cntl_reg:master_conf|stat[9]                                                                                                              ; frontend:front|cntl_reg:master_conf|stat[9]                                                                                                                                   ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|error_reg:master_errc|stat[12]                                                                                                            ; frontend:front|error_reg:master_errc|stat[12]                                                                                                                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|error_reg:master_errc|stat[13]                                                                                                            ; frontend:front|error_reg:master_errc|stat[13]                                                                                                                                 ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|full_dff                               ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|full_dff                                                    ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.167 ; push_msg_cnt[2]                                                                                                                                          ; push_msg_cnt[2]                                                                                                                                                               ; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------+--------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'spi_sck'                                                                                                                                                    ;
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                           ; To Node                                             ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.166 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[1]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.307      ;
; 0.166 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|frame[2]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.307      ;
; 0.172 ; frontend:front|spi_slave:arm|spi_timeout:tout|sclk2 ; frontend:front|spi_slave:arm|spi_timeout:tout|sclk2 ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.314      ;
; 0.173 ; frontend:front|spi_slave:arm|param                  ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.314      ;
; 0.182 ; frontend:front|spi_slave:arm|rx_sr[2]               ; frontend:front|spi_slave:arm|rx_sr[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.324      ;
; 0.183 ; frontend:front|spi_slave:arm|rx_sr[7]               ; frontend:front|spi_slave:arm|rx_sr[8]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.325      ;
; 0.184 ; frontend:front|spi_slave:arm|rx_sr[5]               ; frontend:front|spi_slave:arm|rx_sr[6]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.326      ;
; 0.185 ; frontend:front|spi_slave:arm|rx_sr[4]               ; frontend:front|spi_slave:arm|rx_sr[5]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.327      ;
; 0.186 ; frontend:front|spi_slave:arm|rx_sr[12]              ; frontend:front|spi_slave:arm|rx_sr[13]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.328      ;
; 0.187 ; frontend:front|spi_slave:arm|rx_sr[8]               ; frontend:front|spi_slave:arm|rx_sr[9]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.329      ;
; 0.191 ; frontend:front|spi_slave:arm|rx_sr[1]               ; frontend:front|spi_slave:arm|rx_sr[2]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.333      ;
; 0.194 ; frontend:front|spi_slave:arm|param                  ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.335      ;
; 0.194 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[2]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.335      ;
; 0.195 ; frontend:front|spi_slave:arm|param                  ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.336      ;
; 0.195 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[1]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.336      ;
; 0.199 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.340      ;
; 0.244 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.385      ;
; 0.245 ; frontend:front|spi_slave:arm|tx_sr[11]              ; frontend:front|spi_slave:arm|tx_sr[12]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.386      ;
; 0.245 ; frontend:front|spi_slave:arm|tx_sr[6]               ; frontend:front|spi_slave:arm|tx_sr[7]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.387      ;
; 0.246 ; frontend:front|spi_slave:arm|tx_sr[5]               ; frontend:front|spi_slave:arm|tx_sr[6]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.388      ;
; 0.246 ; frontend:front|spi_slave:arm|rx_sr[9]               ; frontend:front|spi_slave:arm|rx_sr[10]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.388      ;
; 0.247 ; frontend:front|spi_slave:arm|tx_sr[13]              ; frontend:front|spi_slave:arm|tx_sr[14]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.388      ;
; 0.247 ; frontend:front|spi_slave:arm|tx_sr[4]               ; frontend:front|spi_slave:arm|tx_sr[5]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.389      ;
; 0.247 ; frontend:front|spi_slave:arm|tx_sr[3]               ; frontend:front|spi_slave:arm|tx_sr[4]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.389      ;
; 0.247 ; frontend:front|spi_slave:arm|tx_sr[2]               ; frontend:front|spi_slave:arm|tx_sr[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.389      ;
; 0.248 ; frontend:front|spi_slave:arm|tx_sr[10]              ; frontend:front|spi_slave:arm|tx_sr[11]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.389      ;
; 0.248 ; frontend:front|spi_slave:arm|tx_sr[8]               ; frontend:front|spi_slave:arm|tx_sr[9]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.389      ;
; 0.249 ; frontend:front|spi_slave:arm|tx_sr[9]               ; frontend:front|spi_slave:arm|tx_sr[10]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.390      ;
; 0.257 ; frontend:front|spi_slave:arm|rx_sr[10]              ; frontend:front|spi_slave:arm|rx_sr[11]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.399      ;
; 0.257 ; frontend:front|spi_slave:arm|rx_sr[6]               ; frontend:front|spi_slave:arm|rx_sr[7]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.399      ;
; 0.258 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.399      ;
; 0.259 ; frontend:front|spi_slave:arm|rx_sr[14]              ; frontend:front|spi_slave:arm|rx_sr[15]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.400      ;
; 0.261 ; frontend:front|spi_slave:arm|rx_sr[13]              ; frontend:front|spi_slave:arm|rx_sr[14]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.403      ;
; 0.289 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_fetch               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.430      ;
; 0.299 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.440      ;
; 0.305 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.446      ;
; 0.314 ; frontend:front|spi_slave:arm|tx_sr[12]              ; frontend:front|spi_slave:arm|tx_sr[13]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.455      ;
; 0.318 ; frontend:front|spi_slave:arm|rx_sr[11]              ; frontend:front|spi_slave:arm|rx_sr[12]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.460      ;
; 0.327 ; frontend:front|spi_slave:arm|tx_sr[0]               ; frontend:front|spi_slave:arm|tx_sr[1]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.469      ;
; 0.329 ; frontend:front|spi_slave:arm|tx_sr[1]               ; frontend:front|spi_slave:arm|tx_sr[2]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.038      ; 0.471      ;
; 0.335 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.476      ;
; 0.343 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|last                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.484      ;
; 0.346 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.487      ;
; 0.350 ; frontend:front|spi_slave:arm|rx_sr[0]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 0.000        ; 0.041      ; 0.495      ;
; 0.351 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|verylast               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.492      ;
; 0.356 ; frontend:front|spi_slave:arm|rx_sr[0]               ; frontend:front|spi_slave:arm|rx_sr[1]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.041      ; 0.501      ;
; 0.380 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[2]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.521      ;
; 0.399 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.540      ;
; 0.404 ; frontend:front|spi_slave:arm|rx_sr[0]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.041      ; 0.549      ;
; 0.414 ; frontend:front|spi_slave:arm|rx_sr[3]               ; frontend:front|spi_slave:arm|rx_sr[4]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.033      ; 0.551      ;
; 0.441 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.582      ;
; 0.461 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.602      ;
; 0.481 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.622      ;
; 0.543 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.684      ;
; 0.548 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.040      ; 0.692      ;
; 0.574 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.715      ;
; 0.575 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|frame[0]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.716      ;
; 0.599 ; frontend:front|spi_slave:arm|tx_sr[7]               ; frontend:front|spi_slave:arm|tx_sr[8]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.031      ; 0.734      ;
; 0.609 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[7]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.040      ; 0.753      ;
; 0.609 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[6]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.040      ; 0.753      ;
; 0.609 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[5]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.040      ; 0.753      ;
; 0.609 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[4]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.040      ; 0.753      ;
; 0.609 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[3]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.040      ; 0.753      ;
; 0.609 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[2]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.040      ; 0.753      ;
; 0.609 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[1]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.040      ; 0.753      ;
; 0.623 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[14]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.033      ; 0.760      ;
; 0.623 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[13]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.033      ; 0.760      ;
; 0.623 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[12]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.033      ; 0.760      ;
; 0.623 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[11]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.033      ; 0.760      ;
; 0.623 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[10]              ; spi_sck      ; spi_sck     ; 0.000        ; 0.033      ; 0.760      ;
; 0.623 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[9]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.033      ; 0.760      ;
; 0.623 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|tx_sr[8]               ; spi_sck      ; spi_sck     ; 0.000        ; 0.033      ; 0.760      ;
; 0.763 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.904      ;
; 0.763 ; frontend:front|spi_slave:arm|frame[0]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 0.904      ;
; 0.868 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 1.009      ;
; 0.868 ; frontend:front|spi_slave:arm|frame[1]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 1.009      ;
; 0.899 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 1.040      ;
; 0.899 ; frontend:front|spi_slave:arm|frame[3]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 1.040      ;
; 0.900 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|param                  ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 1.041      ;
; 0.900 ; frontend:front|spi_slave:arm|frame[2]               ; frontend:front|spi_slave:arm|addr                   ; spi_sck      ; spi_sck     ; 0.000        ; 0.037      ; 1.041      ;
; 1.192 ; frontend:front|spi_slave:arm|tx_sr[14]              ; frontend:front|spi_slave:arm|miso                   ; spi_sck      ; spi_sck     ; 0.000        ; -0.014     ; 1.256      ;
; 1.439 ; frontend:front|spi_slave:arm|last                   ; frontend:front|spi_slave:arm|miso                   ; spi_sck      ; spi_sck     ; 0.000        ; -0.018     ; 1.499      ;
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'pll0|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                             ;
+--------+--------------+----------------+-----------------+--------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type            ; Clock                                            ; Clock Edge ; Target                                                                                                                                                                        ;
+--------+--------------+----------------+-----------------+--------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a0~porta_address_reg0     ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a12~porta_address_reg0    ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a8~porta_address_reg0     ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a8~porta_we_reg           ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a1~porta_address_reg0     ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a1~porta_we_reg           ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a8~porta_address_reg0     ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a8~porta_we_reg           ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a4~porta_address_reg0     ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a4~porta_we_reg           ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a8~porta_address_reg0     ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a8~porta_we_reg           ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram|ram_block1a0~porta_address_reg0            ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram|ram_block1a0~porta_we_reg                  ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a6~porta_address_reg0     ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a6~porta_we_reg           ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a12~porta_address_reg0    ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a12~porta_we_reg          ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a0~porta_datain_reg0      ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a12~porta_datain_reg0     ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a0~porta_address_reg0 ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a0~porta_we_reg       ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a5~porta_address_reg0 ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a5~porta_we_reg       ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[10]                             ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[11]                             ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[8]                              ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[9]                              ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a0~porta_address_reg0     ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a0~porta_we_reg           ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a4~porta_address_reg0     ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a4~porta_we_reg           ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a8~porta_datain_reg0      ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a8~portb_address_reg0     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[12]                             ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13]                             ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[1]                              ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[3]                              ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[4]                              ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[5]                              ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[8]                              ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[9]                              ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a0~porta_address_reg0     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a0~porta_we_reg           ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a1~porta_datain_reg0      ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a1~portb_address_reg0     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a8~porta_datain_reg0      ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a8~portb_address_reg0     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[10]                             ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[11]                             ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[4]                              ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[5]                              ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[6]                              ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[7]                              ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[8]                              ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[9]                              ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a0~porta_address_reg0     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a0~porta_we_reg           ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a4~porta_datain_reg0      ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a4~portb_address_reg0     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a8~porta_datain_reg0      ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a8~portb_address_reg0     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[0]                              ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[12]                             ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[13]                             ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[14]                             ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15]                             ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[1]                              ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[2]                              ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[3]                              ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a0~portb_address_reg0     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a12~portb_address_reg0    ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a4~porta_address_reg0     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a8~porta_address_reg0     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a1~porta_address_reg0 ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a1~porta_we_reg       ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a9~porta_address_reg0 ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a9~porta_we_reg       ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a12~porta_address_reg0    ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a12~porta_we_reg          ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram|q_b[0]                                     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram|q_b[1]                                     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram|q_b[2]                                     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram|q_b[3]                                     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram|q_b[4]                                     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram|q_b[5]                                     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram|q_b[6]                                     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram|q_b[7]                                     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram|ram_block1a0~porta_datain_reg0             ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; message:msg|uart:uart|fifo8:txfifo|scfifo:scfifo_component|scfifo_ns81:auto_generated|a_dpfifo_6k81:dpfifo|altsyncram_9vf1:FIFOram|ram_block1a0~portb_address_reg0            ;
; 10.169 ; 10.399       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a6~porta_datain_reg0      ;
; 10.169 ; 10.399       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f2|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a12~porta_datain_reg0     ;
; 10.169 ; 10.399       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a0~porta_datain_reg0  ;
; 10.169 ; 10.399       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:hkfifo|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a5~porta_datain_reg0  ;
; 10.169 ; 10.399       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a0~porta_datain_reg0      ;
; 10.169 ; 10.399       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|spi_slave:arm|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a4~porta_datain_reg0      ;
; 10.170 ; 10.400       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[0]                              ;
; 10.170 ; 10.400       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[14]                             ;
; 10.170 ; 10.400       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15]                             ;
; 10.170 ; 10.400       ; 0.230          ; Low Pulse Width ; pll0|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; frontend:front|packetfifo:f1|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[2]                              ;
+--------+--------------+----------------+-----------------+--------------------------------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'spi_sck'                                                                                    ;
+--------+--------------+----------------+------------------+---------+------------+-----------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                              ;
+--------+--------------+----------------+------------------+---------+------------+-----------------------------------------------------+
; 16.454 ; 16.670       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[0]               ;
; 16.454 ; 16.670       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[10]              ;
; 16.454 ; 16.670       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[11]              ;
; 16.454 ; 16.670       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[12]              ;
; 16.454 ; 16.670       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[13]              ;
; 16.454 ; 16.670       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[14]              ;
; 16.454 ; 16.670       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[8]               ;
; 16.454 ; 16.670       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[9]               ;
; 16.455 ; 16.671       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[10]              ;
; 16.455 ; 16.671       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[11]              ;
; 16.455 ; 16.671       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[12]              ;
; 16.455 ; 16.671       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[13]              ;
; 16.455 ; 16.671       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[14]              ;
; 16.455 ; 16.671       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[15]              ;
; 16.455 ; 16.671       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[4]               ;
; 16.455 ; 16.671       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[5]               ;
; 16.455 ; 16.671       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[6]               ;
; 16.455 ; 16.671       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[7]               ;
; 16.455 ; 16.671       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[8]               ;
; 16.455 ; 16.671       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[9]               ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|addr                   ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[0]               ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[1]               ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[2]               ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[3]               ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|last                   ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|param                  ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[1]               ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[2]               ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[3]               ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|spi_timeout:tout|sclk2 ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_fetch               ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[0]               ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[1]               ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[2]               ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[3]               ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[4]               ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[5]               ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[6]               ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[7]               ;
; 16.456 ; 16.672       ; 0.216          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|verylast               ;
; 16.475 ; 16.659       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|addr                   ;
; 16.475 ; 16.659       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[0]               ;
; 16.475 ; 16.659       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[1]               ;
; 16.475 ; 16.659       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[2]               ;
; 16.475 ; 16.659       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|frame[3]               ;
; 16.475 ; 16.659       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|last                   ;
; 16.475 ; 16.659       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|param                  ;
; 16.475 ; 16.659       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_fetch               ;
; 16.475 ; 16.659       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|verylast               ;
; 16.476 ; 16.660       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[1]               ;
; 16.476 ; 16.660       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[2]               ;
; 16.476 ; 16.660       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[3]               ;
; 16.476 ; 16.660       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|spi_timeout:tout|sclk2 ;
; 16.476 ; 16.660       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[0]               ;
; 16.476 ; 16.660       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[1]               ;
; 16.476 ; 16.660       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[2]               ;
; 16.476 ; 16.660       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[3]               ;
; 16.476 ; 16.660       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[4]               ;
; 16.476 ; 16.660       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[5]               ;
; 16.476 ; 16.660       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[6]               ;
; 16.476 ; 16.660       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[7]               ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[0]               ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[10]              ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[11]              ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[12]              ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[13]              ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[14]              ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[15]              ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[4]               ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[5]               ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[6]               ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[7]               ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[8]               ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|rx_sr[9]               ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[10]              ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[11]              ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[12]              ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[13]              ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[14]              ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[8]               ;
; 16.477 ; 16.661       ; 0.184          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|tx_sr[9]               ;
; 16.503 ; 16.658       ; 0.155          ; Low Pulse Width  ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|miso                   ;
; 16.525 ; 16.675       ; 0.150          ; High Pulse Width ; spi_sck ; Fall       ; frontend:front|spi_slave:arm|miso                   ;
; 16.646 ; 16.646       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; spi_sck~inputclkctrl|inclk[0]                       ;
; 16.646 ; 16.646       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; spi_sck~inputclkctrl|outclk                         ;
; 16.654 ; 16.654       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|addr|clk                                  ;
; 16.654 ; 16.654       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|frame[0]|clk                              ;
; 16.654 ; 16.654       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|frame[1]|clk                              ;
; 16.654 ; 16.654       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|frame[2]|clk                              ;
; 16.654 ; 16.654       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|frame[3]|clk                              ;
; 16.654 ; 16.654       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|last|clk                                  ;
; 16.654 ; 16.654       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|param|clk                                 ;
; 16.654 ; 16.654       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|tx_fetch|clk                              ;
; 16.654 ; 16.654       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|verylast|clk                              ;
; 16.655 ; 16.655       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|rx_sr[1]|clk                              ;
; 16.655 ; 16.655       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|rx_sr[2]|clk                              ;
; 16.655 ; 16.655       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|rx_sr[3]|clk                              ;
; 16.655 ; 16.655       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|tout|sclk2|clk                            ;
; 16.655 ; 16.655       ; 0.000          ; High Pulse Width ; spi_sck ; Rise       ; front|arm|tx_sr[0]|clk                              ;
+--------+--------------+----------------+------------------+---------+------------+-----------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'clk_12'                                                                                           ;
+--------+--------------+----------------+------------------+--------+------------+------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock  ; Clock Edge ; Target                                                     ;
+--------+--------------+----------------+------------------+--------+------------+------------------------------------------------------------+
; 41.622 ; 41.622       ; 0.000          ; High Pulse Width ; clk_12 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1]           ;
; 41.622 ; 41.622       ; 0.000          ; High Pulse Width ; clk_12 ; Rise       ; pll0|altpll_component|auto_generated|pll1|observablevcoout ;
; 41.629 ; 41.629       ; 0.000          ; High Pulse Width ; clk_12 ; Rise       ; pll0|altpll_component|auto_generated|pll1|inclk[0]         ;
; 41.637 ; 41.637       ; 0.000          ; High Pulse Width ; clk_12 ; Rise       ; clk_12~input|o                                             ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clk_12 ; Rise       ; clk_12~input|i                                             ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clk_12 ; Rise       ; clk_12~input|i                                             ;
; 41.695 ; 41.695       ; 0.000          ; Low Pulse Width  ; clk_12 ; Rise       ; clk_12~input|o                                             ;
; 41.703 ; 41.703       ; 0.000          ; Low Pulse Width  ; clk_12 ; Rise       ; pll0|altpll_component|auto_generated|pll1|inclk[0]         ;
; 41.710 ; 41.710       ; 0.000          ; Low Pulse Width  ; clk_12 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1]           ;
; 41.710 ; 41.710       ; 0.000          ; Low Pulse Width  ; clk_12 ; Rise       ; pll0|altpll_component|auto_generated|pll1|observablevcoout ;
; 81.050 ; 83.333       ; 2.283          ; Port Rate        ; clk_12 ; Rise       ; clk_12                                                     ;
+--------+--------------+----------------+------------------+--------+------------+------------------------------------------------------------+


+-----------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'clk_T1'                                ;
+--------+--------------+----------------+-----------+--------+------------+--------+
; Slack  ; Actual Width ; Required Width ; Type      ; Clock  ; Clock Edge ; Target ;
+--------+--------------+----------------+-----------+--------+------------+--------+
; 64.384 ; 66.667       ; 2.283          ; Port Rate ; clk_T1 ; Rise       ; clk_T1 ;
+--------+--------------+----------------+-----------+--------+------------+--------+


+----------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                              ;
+-----------+------------+--------+--------+------------+--------------------------------------------------+
; Data Port ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                  ;
+-----------+------------+--------+--------+------------+--------------------------------------------------+
; Rx[*]     ; clk_12     ; -0.750 ; -0.041 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Rx[2]    ; clk_12     ; -0.826 ; -0.130 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Rx[3]    ; clk_12     ; -0.750 ; -0.041 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; spi_mosi  ; spi_sck    ; 0.210  ; 0.053  ; Fall       ; spi_sck                                          ;
+-----------+------------+--------+--------+------------+--------------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                             ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                  ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; Rx[*]     ; clk_12     ; 1.199 ; 0.516 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Rx[2]    ; clk_12     ; 1.199 ; 0.516 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Rx[3]    ; clk_12     ; 1.126 ; 0.430 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; spi_mosi  ; spi_sck    ; 0.002 ; 0.160 ; Fall       ; spi_sck                                          ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                    ;
+-------------+------------+-------+-------+------------+--------------------------------------------------+
; Data Port   ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                  ;
+-------------+------------+-------+-------+------------+--------------------------------------------------+
; Tx[*]       ; clk_12     ; 8.461 ; 8.608 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Tx[1]      ; clk_12     ; 7.307 ; 7.419 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Tx[2]      ; clk_12     ; 8.461 ; 8.608 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; attn        ; clk_12     ; 7.582 ; 7.947 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; spi_miso    ; spi_sck    ; 6.609 ; 6.597 ; Fall       ; spi_sck                                          ;
; spi_miso(n) ; spi_sck    ; 6.597 ; 6.609 ; Fall       ; spi_sck                                          ;
+-------------+------------+-------+-------+------------+--------------------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                            ;
+-------------+------------+-------+-------+------------+--------------------------------------------------+
; Data Port   ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                  ;
+-------------+------------+-------+-------+------------+--------------------------------------------------+
; Tx[*]       ; clk_12     ; 5.989 ; 6.149 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Tx[1]      ; clk_12     ; 5.989 ; 6.149 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Tx[2]      ; clk_12     ; 6.976 ; 7.197 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; attn        ; clk_12     ; 6.958 ; 7.273 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; spi_miso    ; spi_sck    ; 6.550 ; 6.538 ; Fall       ; spi_sck                                          ;
; spi_miso(n) ; spi_sck    ; 6.538 ; 6.550 ; Fall       ; spi_sck                                          ;
+-------------+------------+-------+-------+------------+--------------------------------------------------+


+----------------------------------------------------+
; Propagation Delay                                  ;
+------------+-------------+-------+----+----+-------+
; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
+------------+-------------+-------+----+----+-------+
; Rx[2]      ; Tx[1]       ; 4.660 ;    ;    ; 5.471 ;
; Rx[3]      ; Tx[2]       ; 5.843 ;    ;    ; 6.728 ;
+------------+-------------+-------+----+----+-------+


+----------------------------------------------------+
; Minimum Propagation Delay                          ;
+------------+-------------+-------+----+----+-------+
; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
+------------+-------------+-------+----+----+-------+
; Rx[2]      ; Tx[1]       ; 4.529 ;    ;    ; 5.310 ;
; Rx[3]      ; Tx[2]       ; 5.708 ;    ;    ; 6.577 ;
+------------+-------------+-------+----+----+-------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                           ;
+---------------------------------------------------+--------+-------+----------+---------+---------------------+
; Clock                                             ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+---------------------------------------------------+--------+-------+----------+---------+---------------------+
; Worst-case Slack                                  ; 7.865  ; 0.035 ; N/A      ; N/A     ; 10.058              ;
;  clk_12                                           ; N/A    ; N/A   ; N/A      ; N/A     ; 41.557              ;
;  clk_T1                                           ; N/A    ; N/A   ; N/A      ; N/A     ; 63.542              ;
;  pll0|altpll_component|auto_generated|pll1|clk[1] ; 7.865  ; 0.035 ; N/A      ; N/A     ; 10.058              ;
;  spi_sck                                          ; 29.114 ; 0.166 ; N/A      ; N/A     ; 16.406              ;
; Design-wide TNS                                   ; 0.0    ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  clk_12                                           ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  clk_T1                                           ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  pll0|altpll_component|auto_generated|pll1|clk[1] ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  spi_sck                                          ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
+---------------------------------------------------+--------+-------+----------+---------+---------------------+


+---------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                             ;
+-----------+------------+--------+-------+------------+--------------------------------------------------+
; Data Port ; Clock Port ; Rise   ; Fall  ; Clock Edge ; Clock Reference                                  ;
+-----------+------------+--------+-------+------------+--------------------------------------------------+
; Rx[*]     ; clk_12     ; 0.059  ; 0.265 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Rx[2]    ; clk_12     ; -0.210 ; 0.027 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Rx[3]    ; clk_12     ; 0.059  ; 0.265 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; spi_mosi  ; spi_sck    ; 0.335  ; 0.490 ; Fall       ; spi_sck                                          ;
+-----------+------------+--------+-------+------------+--------------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                             ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                  ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+
; Rx[*]     ; clk_12     ; 1.199 ; 0.804 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Rx[2]    ; clk_12     ; 1.199 ; 0.804 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Rx[3]    ; clk_12     ; 1.126 ; 0.592 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; spi_mosi  ; spi_sck    ; 0.132 ; 0.160 ; Fall       ; spi_sck                                          ;
+-----------+------------+-------+-------+------------+--------------------------------------------------+


+------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                      ;
+-------------+------------+--------+--------+------------+--------------------------------------------------+
; Data Port   ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                  ;
+-------------+------------+--------+--------+------------+--------------------------------------------------+
; Tx[*]       ; clk_12     ; 15.858 ; 15.846 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Tx[1]      ; clk_12     ; 14.036 ; 13.764 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Tx[2]      ; clk_12     ; 15.858 ; 15.846 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; attn        ; clk_12     ; 15.207 ; 14.891 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; spi_miso    ; spi_sck    ; 8.307  ; 8.284  ; Fall       ; spi_sck                                          ;
; spi_miso(n) ; spi_sck    ; 8.284  ; 8.307  ; Fall       ; spi_sck                                          ;
+-------------+------------+--------+--------+------------+--------------------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                            ;
+-------------+------------+-------+-------+------------+--------------------------------------------------+
; Data Port   ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                  ;
+-------------+------------+-------+-------+------------+--------------------------------------------------+
; Tx[*]       ; clk_12     ; 5.989 ; 6.149 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Tx[1]      ; clk_12     ; 5.989 ; 6.149 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
;  Tx[2]      ; clk_12     ; 6.976 ; 7.197 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; attn        ; clk_12     ; 6.958 ; 7.273 ; Rise       ; pll0|altpll_component|auto_generated|pll1|clk[1] ;
; spi_miso    ; spi_sck    ; 6.550 ; 6.538 ; Fall       ; spi_sck                                          ;
; spi_miso(n) ; spi_sck    ; 6.538 ; 6.550 ; Fall       ; spi_sck                                          ;
+-------------+------------+-------+-------+------------+--------------------------------------------------+


+------------------------------------------------------+
; Progagation Delay                                    ;
+------------+-------------+--------+----+----+--------+
; Input Port ; Output Port ; RR     ; RF ; FR ; FF     ;
+------------+-------------+--------+----+----+--------+
; Rx[2]      ; Tx[1]       ; 9.997  ;    ;    ; 10.085 ;
; Rx[3]      ; Tx[2]       ; 12.040 ;    ;    ; 12.227 ;
+------------+-------------+--------+----+----+--------+


+----------------------------------------------------+
; Minimum Progagation Delay                          ;
+------------+-------------+-------+----+----+-------+
; Input Port ; Output Port ; RR    ; RF ; FR ; FF    ;
+------------+-------------+-------+----+----+-------+
; Rx[2]      ; Tx[1]       ; 4.529 ;    ;    ; 5.310 ;
; Rx[3]      ; Tx[2]       ; 5.708 ;    ;    ; 6.577 ;
+------------+-------------+-------+----+----+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                         ;
+--------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; Pin                ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ;
+--------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
; attn               ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[0]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[1]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[2]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[3]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[4]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[5]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[6]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[7]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[8]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[9]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[10]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[11]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[12]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[13]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[14]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[15]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[16]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[17]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[18]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[19]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_a[20]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_ce[2]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_ce[1]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_oe            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_we            ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Tx[2]              ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; Tx[1]              ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; debug[6]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; debug[5]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; debug[4]           ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; FE_port[0]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; FE_port[1]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; FE_port[2]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; FE_port[3]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; FE_port[4]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; FE_port[5]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; FE_port[6]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; FE_port[7]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; FE_port[8]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; FE_port[9]         ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; FE_port[10]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; FE_port[11]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; FE_port[12]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; FE_port[13]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; FE_port[14]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; FE_port[15]        ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_d[0]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_d[1]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_d[2]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_d[3]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_d[4]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_d[5]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_d[6]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; sram_d[7]          ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
; ~ALTERA_CRC_ERROR~ ; 2.5 V        ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ;
+--------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; clk_T1                  ; LVDS         ; 2000 ps         ; 2000 ps         ;
; trigger                 ; LVDS         ; 2000 ps         ; 2000 ps         ;
; Rx[4]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; Rx[1]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; FE_clk                  ; LVDS         ; 2000 ps         ; 2000 ps         ;
; FE_port[0]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; FE_port[1]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; FE_port[2]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; FE_port[3]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; FE_port[4]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; FE_port[5]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; FE_port[6]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; FE_port[7]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; FE_port[8]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; FE_port[9]              ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; FE_port[10]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; FE_port[11]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; FE_port[12]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; FE_port[13]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; FE_port[14]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; FE_port[15]             ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; sram_d[0]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; sram_d[1]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; sram_d[2]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; sram_d[3]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; sram_d[4]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; sram_d[5]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; sram_d[6]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; sram_d[7]               ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; Rx[3]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; Rx[2]                   ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; spi_sck                 ; LVDS         ; 2000 ps         ; 2000 ps         ;
; clk_12                  ; LVDS         ; 2000 ps         ; 2000 ps         ;
; spi_mosi                ; LVDS         ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; ~ALTERA_DCLK~           ; 2.5 V        ; 2000 ps         ; 2000 ps         ;
; clk_T1(n)               ; LVDS         ; 2000 ps         ; 2000 ps         ;
; trigger(n)              ; LVDS         ; 2000 ps         ; 2000 ps         ;
; FE_clk(n)               ; LVDS         ; 2000 ps         ; 2000 ps         ;
; spi_sck(n)              ; LVDS         ; 2000 ps         ; 2000 ps         ;
; clk_12(n)               ; LVDS         ; 2000 ps         ; 2000 ps         ;
; spi_mosi(n)             ; LVDS         ; 2000 ps         ; 2000 ps         ;
+-------------------------+--------------+-----------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; attn               ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.35 V              ; -0.00735 V          ; 0.126 V                              ; 0.011 V                              ; 4.7e-10 s                   ; 4.63e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.35 V             ; -0.00735 V         ; 0.126 V                             ; 0.011 V                             ; 4.7e-10 s                  ; 4.63e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[0]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[1]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[2]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.35 V              ; -0.00735 V          ; 0.126 V                              ; 0.011 V                              ; 4.7e-10 s                   ; 4.63e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.35 V             ; -0.00735 V         ; 0.126 V                             ; 0.011 V                             ; 4.7e-10 s                  ; 4.63e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[3]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.34 V              ; -0.00803 V          ; 0.14 V                               ; 0.045 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.34 V             ; -0.00803 V         ; 0.14 V                              ; 0.045 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[4]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.33 V              ; -0.00219 V          ; 0.108 V                              ; 0.043 V                              ; 3.76e-09 s                  ; 3.48e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.33 V             ; -0.00219 V         ; 0.108 V                             ; 0.043 V                             ; 3.76e-09 s                 ; 3.48e-09 s                 ; Yes                       ; Yes                       ;
; sram_a[5]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[6]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[7]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[8]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.33 V              ; -0.00219 V          ; 0.108 V                              ; 0.043 V                              ; 3.76e-09 s                  ; 3.48e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.33 V             ; -0.00219 V         ; 0.108 V                             ; 0.043 V                             ; 3.76e-09 s                 ; 3.48e-09 s                 ; Yes                       ; Yes                       ;
; sram_a[9]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.34 V              ; -0.00803 V          ; 0.14 V                               ; 0.045 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.34 V             ; -0.00803 V         ; 0.14 V                              ; 0.045 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[10]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.34 V              ; -0.00803 V          ; 0.14 V                               ; 0.045 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.34 V             ; -0.00803 V         ; 0.14 V                              ; 0.045 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[11]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.34 V              ; -0.00803 V          ; 0.14 V                               ; 0.045 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.34 V             ; -0.00803 V         ; 0.14 V                              ; 0.045 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[12]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.34 V              ; -0.00803 V          ; 0.14 V                               ; 0.045 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.34 V             ; -0.00803 V         ; 0.14 V                              ; 0.045 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[13]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.34 V              ; -0.00803 V          ; 0.14 V                               ; 0.045 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.34 V             ; -0.00803 V         ; 0.14 V                              ; 0.045 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[14]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.33 V              ; -0.00219 V          ; 0.108 V                              ; 0.043 V                              ; 3.76e-09 s                  ; 3.48e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.33 V             ; -0.00219 V         ; 0.108 V                             ; 0.043 V                             ; 3.76e-09 s                 ; 3.48e-09 s                 ; Yes                       ; Yes                       ;
; sram_a[15]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[16]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[17]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[18]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[19]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[20]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; sram_ce[2]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.34 V              ; -0.00803 V          ; 0.14 V                               ; 0.045 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.34 V             ; -0.00803 V         ; 0.14 V                              ; 0.045 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; sram_ce[1]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; sram_oe            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; sram_we            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; Tx[2]              ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.33 V              ; -0.00215 V          ; 0.091 V                              ; 0.057 V                              ; 3.77e-09 s                  ; 3.49e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.33 V             ; -0.00215 V         ; 0.091 V                             ; 0.057 V                             ; 3.77e-09 s                 ; 3.49e-09 s                 ; Yes                       ; Yes                       ;
; Tx[1]              ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; debug[6]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.35 V              ; -0.00735 V          ; 0.126 V                              ; 0.011 V                              ; 4.7e-10 s                   ; 4.63e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.35 V             ; -0.00735 V         ; 0.126 V                             ; 0.011 V                             ; 4.7e-10 s                  ; 4.63e-10 s                 ; Yes                       ; Yes                       ;
; debug[5]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.33 V              ; -0.00219 V          ; 0.108 V                              ; 0.043 V                              ; 3.76e-09 s                  ; 3.48e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.33 V             ; -0.00219 V         ; 0.108 V                             ; 0.043 V                             ; 3.76e-09 s                 ; 3.48e-09 s                 ; Yes                       ; Yes                       ;
; debug[4]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.34 V              ; -0.00803 V          ; 0.14 V                               ; 0.045 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.34 V             ; -0.00803 V         ; 0.14 V                              ; 0.045 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[0]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[1]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[2]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[3]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[4]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[5]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[6]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.33 V              ; -0.00215 V          ; 0.091 V                              ; 0.057 V                              ; 3.77e-09 s                  ; 3.49e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.33 V             ; -0.00215 V         ; 0.091 V                             ; 0.057 V                             ; 3.77e-09 s                 ; 3.49e-09 s                 ; Yes                       ; Yes                       ;
; FE_port[7]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[8]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[9]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[10]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[11]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[12]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[13]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.35 V              ; -0.00735 V          ; 0.126 V                              ; 0.011 V                              ; 4.7e-10 s                   ; 4.63e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.35 V             ; -0.00735 V         ; 0.126 V                             ; 0.011 V                             ; 4.7e-10 s                  ; 4.63e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[14]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.35 V              ; -0.00735 V          ; 0.126 V                              ; 0.011 V                              ; 4.7e-10 s                   ; 4.63e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.35 V             ; -0.00735 V         ; 0.126 V                             ; 0.011 V                             ; 4.7e-10 s                  ; 4.63e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[15]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.34 V              ; -0.00803 V          ; 0.14 V                               ; 0.045 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.34 V             ; -0.00803 V         ; 0.14 V                              ; 0.045 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; sram_d[0]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; sram_d[1]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; sram_d[2]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.33 V              ; -0.00215 V          ; 0.091 V                              ; 0.057 V                              ; 3.77e-09 s                  ; 3.49e-09 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.33 V             ; -0.00215 V         ; 0.091 V                             ; 0.057 V                             ; 3.77e-09 s                 ; 3.49e-09 s                 ; Yes                       ; Yes                       ;
; sram_d[3]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.84e-07 V                   ; 2.35 V              ; -0.0105 V           ; 0.143 V                              ; 0.041 V                              ; 4.81e-10 s                  ; 4.81e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 2.84e-07 V                  ; 2.35 V             ; -0.0105 V          ; 0.143 V                             ; 0.041 V                             ; 4.81e-10 s                 ; 4.81e-10 s                 ; Yes                       ; Yes                       ;
; sram_d[4]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.35 V              ; -0.00735 V          ; 0.126 V                              ; 0.011 V                              ; 4.7e-10 s                   ; 4.63e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.35 V             ; -0.00735 V         ; 0.126 V                             ; 0.011 V                             ; 4.7e-10 s                  ; 4.63e-10 s                 ; Yes                       ; Yes                       ;
; sram_d[5]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.34 V              ; -0.00803 V          ; 0.14 V                               ; 0.045 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.34 V             ; -0.00803 V         ; 0.14 V                              ; 0.045 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; sram_d[6]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.34 V              ; -0.00803 V          ; 0.14 V                               ; 0.045 V                              ; 6.89e-10 s                  ; 6.56e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.34 V             ; -0.00803 V         ; 0.14 V                              ; 0.045 V                             ; 6.89e-10 s                 ; 6.56e-10 s                 ; Yes                       ; Yes                       ;
; sram_d[7]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 1.91e-07 V                   ; 2.35 V              ; -0.00735 V          ; 0.126 V                              ; 0.011 V                              ; 4.7e-10 s                   ; 4.63e-10 s                  ; Yes                        ; Yes                        ; 2.32 V                      ; 1.91e-07 V                  ; 2.35 V             ; -0.00735 V         ; 0.126 V                             ; 0.011 V                             ; 4.7e-10 s                  ; 4.63e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_CRC_ERROR~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.32 V                       ; 2.51e-07 V                   ; 2.34 V              ; -0.00726 V          ; 0.108 V                              ; 0.026 V                              ; 6.58e-10 s                  ; 8.2e-10 s                   ; Yes                        ; Yes                        ; 2.32 V                      ; 2.51e-07 V                  ; 2.34 V             ; -0.00726 V         ; 0.108 V                             ; 0.026 V                             ; 6.58e-10 s                 ; 8.2e-10 s                  ; Yes                       ; Yes                       ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin                ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; attn               ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.72 V              ; -0.0401 V           ; 0.163 V                              ; 0.091 V                              ; 2.71e-10 s                  ; 2.61e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.72 V             ; -0.0401 V          ; 0.163 V                             ; 0.091 V                             ; 2.71e-10 s                 ; 2.61e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[0]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[1]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[2]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.72 V              ; -0.0401 V           ; 0.163 V                              ; 0.091 V                              ; 2.71e-10 s                  ; 2.61e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.72 V             ; -0.0401 V          ; 0.163 V                             ; 0.091 V                             ; 2.71e-10 s                 ; 2.61e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[3]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.71 V              ; -0.0352 V           ; 0.147 V                              ; 0.066 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.71 V             ; -0.0352 V          ; 0.147 V                             ; 0.066 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; sram_a[4]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.64 V              ; -0.0118 V           ; 0.201 V                              ; 0.173 V                              ; 2.38e-09 s                  ; 2.19e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.64 V             ; -0.0118 V          ; 0.201 V                             ; 0.173 V                             ; 2.38e-09 s                 ; 2.19e-09 s                 ; No                        ; Yes                       ;
; sram_a[5]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[6]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[7]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[8]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.64 V              ; -0.0118 V           ; 0.201 V                              ; 0.173 V                              ; 2.38e-09 s                  ; 2.19e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.64 V             ; -0.0118 V          ; 0.201 V                             ; 0.173 V                             ; 2.38e-09 s                 ; 2.19e-09 s                 ; No                        ; Yes                       ;
; sram_a[9]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.71 V              ; -0.0352 V           ; 0.147 V                              ; 0.066 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.71 V             ; -0.0352 V          ; 0.147 V                             ; 0.066 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; sram_a[10]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.71 V              ; -0.0352 V           ; 0.147 V                              ; 0.066 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.71 V             ; -0.0352 V          ; 0.147 V                             ; 0.066 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; sram_a[11]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.71 V              ; -0.0352 V           ; 0.147 V                              ; 0.066 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.71 V             ; -0.0352 V          ; 0.147 V                             ; 0.066 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; sram_a[12]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.71 V              ; -0.0352 V           ; 0.147 V                              ; 0.066 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.71 V             ; -0.0352 V          ; 0.147 V                             ; 0.066 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; sram_a[13]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.71 V              ; -0.0352 V           ; 0.147 V                              ; 0.066 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.71 V             ; -0.0352 V          ; 0.147 V                             ; 0.066 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; sram_a[14]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.64 V              ; -0.0118 V           ; 0.201 V                              ; 0.173 V                              ; 2.38e-09 s                  ; 2.19e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.64 V             ; -0.0118 V          ; 0.201 V                             ; 0.173 V                             ; 2.38e-09 s                 ; 2.19e-09 s                 ; No                        ; Yes                       ;
; sram_a[15]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[16]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[17]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[18]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[19]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sram_a[20]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sram_ce[2]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.71 V              ; -0.0352 V           ; 0.147 V                              ; 0.066 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.71 V             ; -0.0352 V          ; 0.147 V                             ; 0.066 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; sram_ce[1]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sram_oe            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sram_we            ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; Tx[2]              ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.64 V              ; -0.0115 V           ; 0.204 V                              ; 0.12 V                               ; 2.38e-09 s                  ; 2.24e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.64 V             ; -0.0115 V          ; 0.204 V                             ; 0.12 V                              ; 2.38e-09 s                 ; 2.24e-09 s                 ; No                        ; Yes                       ;
; Tx[1]              ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; debug[6]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.72 V              ; -0.0401 V           ; 0.163 V                              ; 0.091 V                              ; 2.71e-10 s                  ; 2.61e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.72 V             ; -0.0401 V          ; 0.163 V                             ; 0.091 V                             ; 2.71e-10 s                 ; 2.61e-10 s                 ; Yes                       ; Yes                       ;
; debug[5]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.64 V              ; -0.0118 V           ; 0.201 V                              ; 0.173 V                              ; 2.38e-09 s                  ; 2.19e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.64 V             ; -0.0118 V          ; 0.201 V                             ; 0.173 V                             ; 2.38e-09 s                 ; 2.19e-09 s                 ; No                        ; Yes                       ;
; debug[4]           ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.71 V              ; -0.0352 V           ; 0.147 V                              ; 0.066 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.71 V             ; -0.0352 V          ; 0.147 V                             ; 0.066 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; FE_port[0]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[1]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[2]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[3]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[4]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[5]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[6]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.64 V              ; -0.0115 V           ; 0.204 V                              ; 0.12 V                               ; 2.38e-09 s                  ; 2.24e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.64 V             ; -0.0115 V          ; 0.204 V                             ; 0.12 V                              ; 2.38e-09 s                 ; 2.24e-09 s                 ; No                        ; Yes                       ;
; FE_port[7]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[8]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[9]         ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[10]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[11]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[12]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[13]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.72 V              ; -0.0401 V           ; 0.163 V                              ; 0.091 V                              ; 2.71e-10 s                  ; 2.61e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.72 V             ; -0.0401 V          ; 0.163 V                             ; 0.091 V                             ; 2.71e-10 s                 ; 2.61e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[14]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.72 V              ; -0.0401 V           ; 0.163 V                              ; 0.091 V                              ; 2.71e-10 s                  ; 2.61e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.72 V             ; -0.0401 V          ; 0.163 V                             ; 0.091 V                             ; 2.71e-10 s                 ; 2.61e-10 s                 ; Yes                       ; Yes                       ;
; FE_port[15]        ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.71 V              ; -0.0352 V           ; 0.147 V                              ; 0.066 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.71 V             ; -0.0352 V          ; 0.147 V                             ; 0.066 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; sram_d[0]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sram_d[1]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sram_d[2]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.64 V              ; -0.0115 V           ; 0.204 V                              ; 0.12 V                               ; 2.38e-09 s                  ; 2.24e-09 s                  ; No                         ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.64 V             ; -0.0115 V          ; 0.204 V                             ; 0.12 V                              ; 2.38e-09 s                 ; 2.24e-09 s                 ; No                        ; Yes                       ;
; sram_d[3]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 4.02e-08 V                   ; 2.71 V              ; -0.0351 V           ; 0.173 V                              ; 0.098 V                              ; 2.73e-10 s                  ; 2.69e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 4.02e-08 V                  ; 2.71 V             ; -0.0351 V          ; 0.173 V                             ; 0.098 V                             ; 2.73e-10 s                 ; 2.69e-10 s                 ; Yes                       ; Yes                       ;
; sram_d[4]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.72 V              ; -0.0401 V           ; 0.163 V                              ; 0.091 V                              ; 2.71e-10 s                  ; 2.61e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.72 V             ; -0.0401 V          ; 0.163 V                             ; 0.091 V                             ; 2.71e-10 s                 ; 2.61e-10 s                 ; Yes                       ; Yes                       ;
; sram_d[5]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.71 V              ; -0.0352 V           ; 0.147 V                              ; 0.066 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.71 V             ; -0.0352 V          ; 0.147 V                             ; 0.066 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; sram_d[6]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.71 V              ; -0.0352 V           ; 0.147 V                              ; 0.066 V                              ; 4.51e-10 s                  ; 4.15e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.71 V             ; -0.0352 V          ; 0.147 V                             ; 0.066 V                             ; 4.51e-10 s                 ; 4.15e-10 s                 ; No                        ; Yes                       ;
; sram_d[7]          ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 2.7e-08 V                    ; 2.72 V              ; -0.0401 V           ; 0.163 V                              ; 0.091 V                              ; 2.71e-10 s                  ; 2.61e-10 s                  ; Yes                        ; Yes                        ; 2.62 V                      ; 2.7e-08 V                   ; 2.72 V             ; -0.0401 V          ; 0.163 V                             ; 0.091 V                             ; 2.71e-10 s                 ; 2.61e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_CRC_ERROR~ ; 2.5 V        ; 0 s                 ; 0 s                 ; 2.62 V                       ; 3.52e-08 V                   ; 2.7 V               ; -0.012 V            ; 0.274 V                              ; 0.034 V                              ; 3.18e-10 s                  ; 4.96e-10 s                  ; No                         ; Yes                        ; 2.62 V                      ; 3.52e-08 V                  ; 2.7 V              ; -0.012 V           ; 0.274 V                             ; 0.034 V                             ; 3.18e-10 s                 ; 4.96e-10 s                 ; No                        ; Yes                       ;
+--------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                       ;
+--------------------------------------------------+--------------------------------------------------+----------+------------+------------+------------+
; From Clock                                       ; To Clock                                         ; RR Paths ; FR Paths   ; RF Paths   ; FF Paths   ;
+--------------------------------------------------+--------------------------------------------------+----------+------------+------------+------------+
; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 23979    ; 116        ; 0          ; 3          ;
; spi_sck                                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0        ; false path ; 0          ; false path ;
; pll0|altpll_component|auto_generated|pll1|clk[1] ; spi_sck                                          ; 0        ; 0          ; false path ; 0          ;
; spi_sck                                          ; spi_sck                                          ; 0        ; 0          ; 0          ; 82         ;
+--------------------------------------------------+--------------------------------------------------+----------+------------+------------+------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                        ;
+--------------------------------------------------+--------------------------------------------------+----------+------------+------------+------------+
; From Clock                                       ; To Clock                                         ; RR Paths ; FR Paths   ; RF Paths   ; FF Paths   ;
+--------------------------------------------------+--------------------------------------------------+----------+------------+------------+------------+
; pll0|altpll_component|auto_generated|pll1|clk[1] ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 23979    ; 116        ; 0          ; 3          ;
; spi_sck                                          ; pll0|altpll_component|auto_generated|pll1|clk[1] ; 0        ; false path ; 0          ; false path ;
; pll0|altpll_component|auto_generated|pll1|clk[1] ; spi_sck                                          ; 0        ; 0          ; false path ; 0          ;
; spi_sck                                          ; spi_sck                                          ; 0        ; 0          ; 0          ; 82         ;
+--------------------------------------------------+--------------------------------------------------+----------+------------+------------+------------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 3     ; 3    ;
; Unconstrained Input Port Paths  ; 5     ; 5    ;
; Unconstrained Output Ports      ; 5     ; 5    ;
; Unconstrained Output Port Paths ; 12    ; 12   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
    Info: Version 9.1 Build 304 01/25/2010 Service Pack 1 SJ Web Edition
    Info: Copyright (C) 1991-2010 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer to the 
    Info: applicable agreement for further details.
    Info: Processing started: Tue May 17 08:58:30 2011
Info: Command: quartus_sta sirena.qpf
Info: qsta_default_script.tcl version: #1
Info: Core supply voltage is 1.2V
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Reading SDC File: 'sirena.sdc'
Info: Deriving PLL Clocks
    Info: create_generated_clock -source {pll0|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -phase 17.31 -duty_cycle 50.00 -name {pll0|altpll_component|auto_generated|pll1|clk[1]} {pll0|altpll_component|auto_generated|pll1|clk[1]}
Info: Clock uncertainty calculation is delayed until the next update_timing_netlist call
Info: Deriving Clock Uncertainty
    Info: set_clock_uncertainty -rise_from [get_clocks {spi_sck}] -rise_to [get_clocks {spi_sck}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {spi_sck}] -fall_to [get_clocks {spi_sck}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {spi_sck}] -rise_to [get_clocks {spi_sck}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {spi_sck}] -fall_to [get_clocks {spi_sck}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {spi_sck}] -rise_to [get_clocks {spi_sck}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {spi_sck}] -fall_to [get_clocks {spi_sck}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {spi_sck}] -rise_to [get_clocks {spi_sck}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {spi_sck}] -fall_to [get_clocks {spi_sck}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.020
Info: Analyzing Slow 1200mV 85C Model
Info: Worst-case setup slack is 7.865
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     7.865         0.000 pll0|altpll_component|auto_generated|pll1|clk[1] 
    Info:    29.114         0.000 spi_sck 
Info: Worst-case hold slack is 0.160
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.160         0.000 pll0|altpll_component|auto_generated|pll1|clk[1] 
    Info:     0.436         0.000 spi_sck 
Info: No Recovery paths to report
Info: No Removal paths to report
Info: Worst-case minimum pulse width slack is 10.081
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    10.081         0.000 pll0|altpll_component|auto_generated|pll1|clk[1] 
    Info:    16.414         0.000 spi_sck 
    Info:    41.557         0.000 clk_12 
    Info:    63.542         0.000 clk_T1 
Info: Report Timing: Found 1 setup paths (0 violated).  Worst case slack is 7.865
    Info: -to_clock [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}]
    Info: -setup
    Info: -stdout
Info: Path #1: Setup slack is 7.865 
    Info: ===================================================================
    Info: From Node    : frontend:front|spi_slave:arm|frame_done_n[1]
    Info: To Node      : frontend:front|spi_slave:arm|rx_exec
    Info: Launch Clock : pll0|altpll_component|auto_generated|pll1|clk[1] (INVERTED)
    Info: Latch Clock  : pll0|altpll_component|auto_generated|pll1|clk[1]
    Info: 
    Info: Data Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     11.417     11.417           launch edge time
    Info:     17.510      6.093  F        clock network delay
    Info:     17.771      0.261     uTco  frontend:front|spi_slave:arm|frame_done_n[1]
    Info:     17.771      0.000 FF  CELL  front|arm|frame_done_n[1]|q
    Info:     18.150      0.379 FF    IC  front|arm|rx_data[4]~1|datad
    Info:     18.318      0.168 FR  CELL  front|arm|rx_data[4]~1|combout
    Info:     19.151      0.833 RR    IC  front|arm|rx_exec~0|datac
    Info:     19.478      0.327 RR  CELL  front|arm|rx_exec~0|combout
    Info:     19.478      0.000 RR    IC  front|arm|rx_exec|d
    Info:     19.577      0.099 RR  CELL  frontend:front|spi_slave:arm|rx_exec
    Info: 
    Info: Data Required Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     21.834     21.834           latch edge time
    Info:     27.112      5.278  R        clock network delay
    Info:     27.441      0.329           clock pessimism
    Info:     27.421     -0.020           clock uncertainty
    Info:     27.442      0.021     uTsu  frontend:front|spi_slave:arm|rx_exec
    Info: 
    Info: Data Arrival Time  :    19.577
    Info: Data Required Time :    27.442
    Info: Slack              :     7.865 
    Info: ===================================================================
    Info: 
Info: Report Timing: Found 1 setup paths (0 violated).  Worst case slack is 29.114
    Info: -to_clock [get_clocks {spi_sck}]
    Info: -setup
    Info: -stdout
Info: Path #1: Setup slack is 29.114 
    Info: ===================================================================
    Info: From Node    : frontend:front|spi_slave:arm|last
    Info: To Node      : frontend:front|spi_slave:arm|miso
    Info: Launch Clock : spi_sck (INVERTED)
    Info: Latch Clock  : spi_sck (INVERTED)
    Info: 
    Info: Data Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     16.666     16.666           launch edge time
    Info:     19.574      2.908  F        clock network delay
    Info:     19.835      0.261     uTco  frontend:front|spi_slave:arm|last
    Info:     19.835      0.000 FF  CELL  front|arm|last|q
    Info:     20.801      0.966 FF    IC  front|arm|miso~SLOAD_MUX|datab
    Info:     21.295      0.494 FR  CELL  front|arm|miso~SLOAD_MUX|combout
    Info:     23.087      1.792 RR    IC  front|arm|miso|d
    Info:     23.532      0.445 RR  CELL  frontend:front|spi_slave:arm|miso
    Info: 
    Info: Data Required Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     49.999     49.999           latch edge time
    Info:     52.717      2.718  F        clock network delay
    Info:     52.775      0.058           clock pessimism
    Info:     52.755     -0.020           clock uncertainty
    Info:     52.646     -0.109     uTsu  frontend:front|spi_slave:arm|miso
    Info: 
    Info: Data Arrival Time  :    23.532
    Info: Data Required Time :    52.646
    Info: Slack              :    29.114 
    Info: ===================================================================
    Info: 
Info: Report Timing: Found 1 hold paths (0 violated).  Worst case slack is 0.160
    Info: -to_clock [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}]
    Info: -hold
    Info: -stdout
Info: Path #1: Hold slack is 0.160 
    Info: ===================================================================
    Info: From Node    : frontend:front|spi_slave:arm|rx_d_p[9]
    Info: To Node      : frontend:front|spi_slave:arm|rx_data[9]
    Info: Launch Clock : pll0|altpll_component|auto_generated|pll1|clk[1]
    Info: Latch Clock  : pll0|altpll_component|auto_generated|pll1|clk[1]
    Info: 
    Info: Data Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:      1.001      1.001           launch edge time
    Info:      6.293      5.292  R        clock network delay
    Info:      6.554      0.261     uTco  frontend:front|spi_slave:arm|rx_d_p[9]
    Info:      6.554      0.000 FF  CELL  front|arm|rx_d_p[9]|q
    Info:      7.050      0.496 FF    IC  front|arm|rx_data~10|datad
    Info:      7.183      0.133 FF  CELL  front|arm|rx_data~10|combout
    Info:      7.183      0.000 FF    IC  front|arm|rx_data[9]|d
    Info:      7.266      0.083 FF  CELL  frontend:front|spi_slave:arm|rx_data[9]
    Info: 
    Info: Data Required Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:      1.001      1.001           latch edge time
    Info:      7.205      6.204  R        clock network delay
    Info:      6.874     -0.331           clock pessimism
    Info:      6.894      0.020           clock uncertainty
    Info:      7.106      0.212      uTh  frontend:front|spi_slave:arm|rx_data[9]
    Info: 
    Info: Data Arrival Time  :     7.266
    Info: Data Required Time :     7.106
    Info: Slack              :     0.160 
    Info: ===================================================================
    Info: 
Info: Report Timing: Found 1 hold paths (0 violated).  Worst case slack is 0.436
    Info: -to_clock [get_clocks {spi_sck}]
    Info: -hold
    Info: -stdout
Info: Path #1: Hold slack is 0.436 
    Info: ===================================================================
    Info: From Node    : frontend:front|spi_slave:arm|frame[1]
    Info: To Node      : frontend:front|spi_slave:arm|frame[1]
    Info: Launch Clock : spi_sck (INVERTED)
    Info: Latch Clock  : spi_sck (INVERTED)
    Info: 
    Info: Data Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     16.666     16.666           launch edge time
    Info:     19.438      2.772  F        clock network delay
    Info:     19.699      0.261     uTco  frontend:front|spi_slave:arm|frame[1]
    Info:     19.699      0.000 FF  CELL  front|arm|frame[1]|q
    Info:     19.699      0.000 FF    IC  front|arm|frame[1]~0|datac
    Info:     20.101      0.402 FF  CELL  front|arm|frame[1]~0|combout
    Info:     20.101      0.000 FF    IC  front|arm|frame[1]|d
    Info:     20.184      0.083 FF  CELL  frontend:front|spi_slave:arm|frame[1]
    Info: 
    Info: Data Required Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     16.666     16.666           latch edge time
    Info:     19.574      2.908  F        clock network delay
    Info:     19.516     -0.058           clock pessimism
    Info:     19.536      0.020           clock uncertainty
    Info:     19.748      0.212      uTh  frontend:front|spi_slave:arm|frame[1]
    Info: 
    Info: Data Arrival Time  :    20.184
    Info: Data Required Time :    19.748
    Info: Slack              :     0.436 
    Info: ===================================================================
    Info: 
Info: Report Minimum Pulse Width: Found 1 results (0 violated).  Worst case slack is 10.081
    Info: Targets: [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1...]
    Info: -nworst: 1
    Info: -detail: full_path
Info: Path #1: slack is 10.081 
    Info: ===================================================================
    Info: Node             : cntr_array:cntrs|cntr_reg:cntr[1].c|latch[16]
    Info: Clock            : pll0|altpll_component|auto_generated|pll1|clk[1]
    Info: Type             : High Pulse Width
    Info: 
    Info: Late Clock Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:      1.001      1.001           launch edge time
    Info:      1.001      0.000           source latency
    Info:      1.001      0.000           clk_12
    Info:      1.001      0.000 RR    IC  clk_12~input|i
    Info:      1.922      0.921 RR  CELL  clk_12~input|o
    Info:      4.279      2.357 RR    IC  pll0|altpll_component|auto_generated|pll1|inclk[0]
    Info:      2.416     -1.863 RR  CELL  pll0|altpll_component|auto_generated|pll1|observablevcoout
    Info:      2.416      0.000 RR  CELL  pll0|altpll_component|auto_generated|pll1|clk[1]
    Info:      4.781      2.365 RR    IC  pll0|altpll_component|auto_generated|clk[1]~clkctrl|inclk[0]
    Info:      4.781      0.000 RR  CELL  pll0|altpll_component|auto_generated|clk[1]~clkctrl|outclk
    Info:      6.484      1.703 RR    IC  cntrs|cntr[1].c|latch[16]|clk
    Info:      7.151      0.667 RR  CELL  cntr_array:cntrs|cntr_reg:cntr[1].c|latch[16]
    Info: 
    Info: Early Clock Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     11.417     11.417           launch edge time
    Info:     11.417      0.000           source latency
    Info:     11.417      0.000           clk_12
    Info:     11.417      0.000 RR    IC  clk_12~input|i
    Info:     12.304      0.887 RR  CELL  clk_12~input|o
    Info:     14.567      2.263 RR    IC  pll0|altpll_component|auto_generated|pll1|inclk[0]
    Info:     12.616     -1.951 RR  CELL  pll0|altpll_component|auto_generated|pll1|observablevcoout
    Info:     12.616      0.000 RR  CELL  pll0|altpll_component|auto_generated|pll1|clk[1]
    Info:     14.854      2.238 FF    IC  pll0|altpll_component|auto_generated|clk[1]~clkctrl|inclk[0]
    Info:     14.854      0.000 FF  CELL  pll0|altpll_component|auto_generated|clk[1]~clkctrl|outclk
    Info:     16.458      1.604 FF    IC  cntrs|cntr[1].c|latch[16]|clk
    Info:     17.028      0.570 FF  CELL  cntr_array:cntrs|cntr_reg:cntr[1].c|latch[16]
    Info:     17.452      0.424           clock pessimism
    Info: 
    Info: Required Width   :     0.220
    Info: Actual Width     :    10.301
    Info: Slack            :    10.081
    Info: ===================================================================
    Info: 
Info: Report Minimum Pulse Width: Found 1 results (0 violated).  Worst case slack is 16.414
    Info: Targets: [get_clocks {spi_sck}]
    Info: -nworst: 1
    Info: -detail: full_path
Info: Path #1: slack is 16.414 
    Info: ===================================================================
    Info: Node             : frontend:front|spi_slave:arm|addr
    Info: Clock            : spi_sck (INVERTED)
    Info: Type             : Low Pulse Width
    Info: 
    Info: Late Clock Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:      0.000      0.000           launch edge time
    Info:      0.000      0.000           source latency
    Info:      0.000      0.000           spi_sck
    Info:      0.000      0.000 RR    IC  spi_sck~input|i
    Info:      0.874      0.874 RR  CELL  spi_sck~input|o
    Info:      1.064      0.190 RR    IC  spi_sck~inputclkctrl|inclk[0]
    Info:      1.064      0.000 RR  CELL  spi_sck~inputclkctrl|outclk
    Info:      2.292      1.228 RR    IC  front|arm|addr|clk
    Info:      2.972      0.680 RF  CELL  frontend:front|spi_slave:arm|addr
    Info: 
    Info: Early Clock Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     16.666     16.666           launch edge time
    Info:     16.666      0.000           source latency
    Info:     16.666      0.000           spi_sck
    Info:     16.666      0.000 FF    IC  spi_sck~input|i
    Info:     17.483      0.817 FF  CELL  spi_sck~input|o
    Info:     17.655      0.172 FF    IC  spi_sck~inputclkctrl|inclk[0]
    Info:     17.655      0.000 FF  CELL  spi_sck~inputclkctrl|outclk
    Info:     18.828      1.173 FF    IC  front|arm|addr|clk
    Info:     19.438      0.610 FR  CELL  frontend:front|spi_slave:arm|addr
    Info:     19.574      0.136           clock pessimism
    Info: 
    Info: Required Width   :     0.188
    Info: Actual Width     :    16.602
    Info: Slack            :    16.414
    Info: ===================================================================
    Info: 
Info: Report Minimum Pulse Width: Found 1 results (0 violated).  Worst case slack is 41.557
    Info: Targets: [get_clocks {clk_12}]
    Info: -nworst: 1
    Info: -detail: full_path
Info: Path #1: slack is 41.557 
    Info: ===================================================================
    Info: Node             : pll0|altpll_component|auto_generated|pll1|inclk[0]
    Info: Clock            : clk_12
    Info: Type             : High Pulse Width
    Info: 
    Info: Late Clock Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:      0.000      0.000           launch edge time
    Info:      0.000      0.000           source latency
    Info:      0.000      0.000           clk_12
    Info:      0.000      0.000 RR    IC  clk_12~input|i
    Info:      0.921      0.921 RR  CELL  clk_12~input|o
    Info:      3.278      2.357 RR    IC  pll0|altpll_component|auto_generated|pll1|inclk[0]
    Info: 
    Info: Early Clock Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     41.666     41.666           launch edge time
    Info:     41.666      0.000           source latency
    Info:     41.666      0.000           clk_12
    Info:     41.666      0.000 FF    IC  clk_12~input|i
    Info:     42.479      0.813 FF  CELL  clk_12~input|o
    Info:     44.710      2.231 FF    IC  pll0|altpll_component|auto_generated|pll1|inclk[0]
    Info:     44.835      0.125           clock pessimism
    Info: 
    Info: Required Width   :     0.000
    Info: Actual Width     :    41.557
    Info: Slack            :    41.557
    Info: ===================================================================
    Info: 
Info: Report Minimum Pulse Width: Found 1 results (0 violated).  Worst case slack is 63.542
    Info: Targets: [get_clocks {clk_T1}]
    Info: -nworst: 1
    Info: -detail: full_path
Info: Path #1: slack is 63.542 
    Info: ===================================================================
    Info: Node             : clk_T1
    Info: Clock            : clk_T1
    Info: Type             : Port Rate
    Info: Required Width   :     3.125
    Info: Actual Width     :    66.667
    Info: Slack            :    63.542
    Info: ===================================================================
    Info: 
Info: Analyzing Slow 1200mV 0C Model
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Deriving Clock Uncertainty
    Info: set_clock_uncertainty -rise_from [get_clocks {spi_sck}] -rise_to [get_clocks {spi_sck}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {spi_sck}] -fall_to [get_clocks {spi_sck}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {spi_sck}] -rise_to [get_clocks {spi_sck}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {spi_sck}] -fall_to [get_clocks {spi_sck}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {spi_sck}] -rise_to [get_clocks {spi_sck}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {spi_sck}] -fall_to [get_clocks {spi_sck}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {spi_sck}] -rise_to [get_clocks {spi_sck}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {spi_sck}] -fall_to [get_clocks {spi_sck}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.020
Info: Worst-case setup slack is 8.077
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     8.077         0.000 pll0|altpll_component|auto_generated|pll1|clk[1] 
    Info:    29.385         0.000 spi_sck 
Info: Worst-case hold slack is 0.113
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.113         0.000 pll0|altpll_component|auto_generated|pll1|clk[1] 
    Info:     0.386         0.000 spi_sck 
Info: No Recovery paths to report
Info: No Removal paths to report
Info: Worst-case minimum pulse width slack is 10.058
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    10.058         0.000 pll0|altpll_component|auto_generated|pll1|clk[1] 
    Info:    16.406         0.000 spi_sck 
    Info:    41.567         0.000 clk_12 
    Info:    63.542         0.000 clk_T1 
Info: Report Timing: Found 1 setup paths (0 violated).  Worst case slack is 8.077
    Info: -to_clock [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}]
    Info: -setup
    Info: -stdout
Info: Path #1: Setup slack is 8.077 
    Info: ===================================================================
    Info: From Node    : frontend:front|spi_slave:arm|frame_done_n[1]
    Info: To Node      : frontend:front|spi_slave:arm|rx_exec
    Info: Launch Clock : pll0|altpll_component|auto_generated|pll1|clk[1] (INVERTED)
    Info: Latch Clock  : pll0|altpll_component|auto_generated|pll1|clk[1]
    Info: 
    Info: Data Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     11.417     11.417           launch edge time
    Info:     16.795      5.378  F        clock network delay
    Info:     17.035      0.240     uTco  frontend:front|spi_slave:arm|frame_done_n[1]
    Info:     17.035      0.000 FF  CELL  front|arm|frame_done_n[1]|q
    Info:     17.378      0.343 FF    IC  front|arm|rx_data[4]~1|datad
    Info:     17.529      0.151 FR  CELL  front|arm|rx_data[4]~1|combout
    Info:     18.334      0.805 RR    IC  front|arm|rx_exec~0|datac
    Info:     18.639      0.305 RR  CELL  front|arm|rx_exec~0|combout
    Info:     18.639      0.000 RR    IC  front|arm|rx_exec|d
    Info:     18.729      0.090 RR  CELL  frontend:front|spi_slave:arm|rx_exec
    Info: 
    Info: Data Required Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     21.834     21.834           latch edge time
    Info:     26.516      4.682  R        clock network delay
    Info:     26.804      0.288           clock pessimism
    Info:     26.784     -0.020           clock uncertainty
    Info:     26.806      0.022     uTsu  frontend:front|spi_slave:arm|rx_exec
    Info: 
    Info: Data Arrival Time  :    18.729
    Info: Data Required Time :    26.806
    Info: Slack              :     8.077 
    Info: ===================================================================
    Info: 
Info: Report Timing: Found 1 setup paths (0 violated).  Worst case slack is 29.385
    Info: -to_clock [get_clocks {spi_sck}]
    Info: -setup
    Info: -stdout
Info: Path #1: Setup slack is 29.385 
    Info: ===================================================================
    Info: From Node    : frontend:front|spi_slave:arm|last
    Info: To Node      : frontend:front|spi_slave:arm|miso
    Info: Launch Clock : spi_sck (INVERTED)
    Info: Latch Clock  : spi_sck (INVERTED)
    Info: 
    Info: Data Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     16.666     16.666           launch edge time
    Info:     19.258      2.592  F        clock network delay
    Info:     19.498      0.240     uTco  frontend:front|spi_slave:arm|last
    Info:     19.498      0.000 RR  CELL  front|arm|last|q
    Info:     20.445      0.947 RR    IC  front|arm|miso~SLOAD_MUX|datab
    Info:     20.825      0.380 RR  CELL  front|arm|miso~SLOAD_MUX|combout
    Info:     22.583      1.758 RR    IC  front|arm|miso|d
    Info:     22.980      0.397 RR  CELL  frontend:front|spi_slave:arm|miso
    Info: 
    Info: Data Required Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     49.999     49.999           latch edge time
    Info:     52.437      2.438  F        clock network delay
    Info:     52.489      0.052           clock pessimism
    Info:     52.469     -0.020           clock uncertainty
    Info:     52.365     -0.104     uTsu  frontend:front|spi_slave:arm|miso
    Info: 
    Info: Data Arrival Time  :    22.980
    Info: Data Required Time :    52.365
    Info: Slack              :    29.385 
    Info: ===================================================================
    Info: 
Info: Report Timing: Found 1 hold paths (0 violated).  Worst case slack is 0.113
    Info: -to_clock [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}]
    Info: -hold
    Info: -stdout
Info: Path #1: Hold slack is 0.113 
    Info: ===================================================================
    Info: From Node    : frontend:front|spi_slave:arm|rx_d_p[9]
    Info: To Node      : frontend:front|spi_slave:arm|rx_data[9]
    Info: Launch Clock : pll0|altpll_component|auto_generated|pll1|clk[1]
    Info: Latch Clock  : pll0|altpll_component|auto_generated|pll1|clk[1]
    Info: 
    Info: Data Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:      1.001      1.001           launch edge time
    Info:      5.692      4.691  R        clock network delay
    Info:      5.932      0.240     uTco  frontend:front|spi_slave:arm|rx_d_p[9]
    Info:      5.932      0.000 FF  CELL  front|arm|rx_d_p[9]|q
    Info:      6.375      0.443 FF    IC  front|arm|rx_data~10|datad
    Info:      6.491      0.116 FF  CELL  front|arm|rx_data~10|combout
    Info:      6.491      0.000 FF    IC  front|arm|rx_data[9]|d
    Info:      6.563      0.072 FF  CELL  frontend:front|spi_slave:arm|rx_data[9]
    Info: 
    Info: Data Required Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:      1.001      1.001           latch edge time
    Info:      6.524      5.523  R        clock network delay
    Info:      6.235     -0.289           clock pessimism
    Info:      6.255      0.020           clock uncertainty
    Info:      6.450      0.195      uTh  frontend:front|spi_slave:arm|rx_data[9]
    Info: 
    Info: Data Arrival Time  :     6.563
    Info: Data Required Time :     6.450
    Info: Slack              :     0.113 
    Info: ===================================================================
    Info: 
Info: Report Timing: Found 1 hold paths (0 violated).  Worst case slack is 0.386
    Info: -to_clock [get_clocks {spi_sck}]
    Info: -hold
    Info: -stdout
Info: Path #1: Hold slack is 0.386 
    Info: ===================================================================
    Info: From Node    : frontend:front|spi_slave:arm|frame[1]
    Info: To Node      : frontend:front|spi_slave:arm|frame[1]
    Info: Launch Clock : spi_sck (INVERTED)
    Info: Latch Clock  : spi_sck (INVERTED)
    Info: 
    Info: Data Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     16.666     16.666           launch edge time
    Info:     19.138      2.472  F        clock network delay
    Info:     19.378      0.240     uTco  frontend:front|spi_slave:arm|frame[1]
    Info:     19.378      0.000 FF  CELL  front|arm|frame[1]|q
    Info:     19.378      0.000 FF    IC  front|arm|frame[1]~0|datac
    Info:     19.735      0.357 FF  CELL  front|arm|frame[1]~0|combout
    Info:     19.735      0.000 FF    IC  front|arm|frame[1]|d
    Info:     19.807      0.072 FF  CELL  frontend:front|spi_slave:arm|frame[1]
    Info: 
    Info: Data Required Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     16.666     16.666           latch edge time
    Info:     19.258      2.592  F        clock network delay
    Info:     19.206     -0.052           clock pessimism
    Info:     19.226      0.020           clock uncertainty
    Info:     19.421      0.195      uTh  frontend:front|spi_slave:arm|frame[1]
    Info: 
    Info: Data Arrival Time  :    19.807
    Info: Data Required Time :    19.421
    Info: Slack              :     0.386 
    Info: ===================================================================
    Info: 
Info: Report Minimum Pulse Width: Found 1 results (0 violated).  Worst case slack is 10.058
    Info: Targets: [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1...]
    Info: -nworst: 1
    Info: -detail: full_path
Info: Path #1: slack is 10.058 
    Info: ===================================================================
    Info: Node             : frontend:front|packetfifo:hkfifo|rd[0]
    Info: Clock            : pll0|altpll_component|auto_generated|pll1|clk[1]
    Info: Type             : High Pulse Width
    Info: 
    Info: Late Clock Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:      1.001      1.001           launch edge time
    Info:      1.001      0.000           source latency
    Info:      1.001      0.000           clk_12
    Info:      1.001      0.000 RR    IC  clk_12~input|i
    Info:      1.836      0.835 RR  CELL  clk_12~input|o
    Info:      3.911      2.075 RR    IC  pll0|altpll_component|auto_generated|pll1|inclk[0]
    Info:      2.277     -1.634 RR  CELL  pll0|altpll_component|auto_generated|pll1|observablevcoout
    Info:      2.277      0.000 RR  CELL  pll0|altpll_component|auto_generated|pll1|clk[1]
    Info:      4.342      2.065 RR    IC  pll0|altpll_component|auto_generated|clk[1]~clkctrl|inclk[0]
    Info:      4.342      0.000 RR  CELL  pll0|altpll_component|auto_generated|clk[1]~clkctrl|outclk
    Info:      5.911      1.569 RR    IC  front|hkfifo|rd[0]|clk
    Info:      6.523      0.612 RR  CELL  frontend:front|packetfifo:hkfifo|rd[0]
    Info: 
    Info: Early Clock Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     11.417     11.417           launch edge time
    Info:     11.417      0.000           source latency
    Info:     11.417      0.000           clk_12
    Info:     11.417      0.000 RR    IC  clk_12~input|i
    Info:     12.221      0.804 RR  CELL  clk_12~input|o
    Info:     14.213      1.992 RR    IC  pll0|altpll_component|auto_generated|pll1|inclk[0]
    Info:     12.504     -1.709 RR  CELL  pll0|altpll_component|auto_generated|pll1|observablevcoout
    Info:     12.504      0.000 RR  CELL  pll0|altpll_component|auto_generated|pll1|clk[1]
    Info:     14.453      1.949 FF    IC  pll0|altpll_component|auto_generated|clk[1]~clkctrl|inclk[0]
    Info:     14.453      0.000 FF  CELL  pll0|altpll_component|auto_generated|clk[1]~clkctrl|outclk
    Info:     15.908      1.455 FF    IC  front|hkfifo|rd[0]|clk
    Info:     16.425      0.517 FF  CELL  frontend:front|packetfifo:hkfifo|rd[0]
    Info:     16.797      0.372           clock pessimism
    Info: 
    Info: Required Width   :     0.216
    Info: Actual Width     :    10.274
    Info: Slack            :    10.058
    Info: ===================================================================
    Info: 
Info: Report Minimum Pulse Width: Found 1 results (0 violated).  Worst case slack is 16.406
    Info: Targets: [get_clocks {spi_sck}]
    Info: -nworst: 1
    Info: -detail: full_path
Info: Path #1: slack is 16.406 
    Info: ===================================================================
    Info: Node             : frontend:front|spi_slave:arm|rx_sr[1]
    Info: Clock            : spi_sck (INVERTED)
    Info: Type             : Low Pulse Width
    Info: 
    Info: Late Clock Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:      0.000      0.000           launch edge time
    Info:      0.000      0.000           source latency
    Info:      0.000      0.000           spi_sck
    Info:      0.000      0.000 RR    IC  spi_sck~input|i
    Info:      0.792      0.792 RR  CELL  spi_sck~input|o
    Info:      0.958      0.166 RR    IC  spi_sck~inputclkctrl|inclk[0]
    Info:      0.958      0.000 RR  CELL  spi_sck~inputclkctrl|outclk
    Info:      2.037      1.079 RR    IC  front|arm|rx_sr[1]|clk
    Info:      2.667      0.630 RF  CELL  frontend:front|spi_slave:arm|rx_sr[1]
    Info: 
    Info: Early Clock Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     16.666     16.666           launch edge time
    Info:     16.666      0.000           source latency
    Info:     16.666      0.000           spi_sck
    Info:     16.666      0.000 FF    IC  spi_sck~input|i
    Info:     17.401      0.735 FF  CELL  spi_sck~input|o
    Info:     17.557      0.156 FF    IC  spi_sck~inputclkctrl|inclk[0]
    Info:     17.557      0.000 FF  CELL  spi_sck~inputclkctrl|outclk
    Info:     18.589      1.032 FF    IC  front|arm|rx_sr[1]|clk
    Info:     19.137      0.548 FR  CELL  frontend:front|spi_slave:arm|rx_sr[1]
    Info:     19.257      0.120           clock pessimism
    Info: 
    Info: Required Width   :     0.184
    Info: Actual Width     :    16.590
    Info: Slack            :    16.406
    Info: ===================================================================
    Info: 
Info: Report Minimum Pulse Width: Found 1 results (0 violated).  Worst case slack is 41.567
    Info: Targets: [get_clocks {clk_12}]
    Info: -nworst: 1
    Info: -detail: full_path
Info: Path #1: slack is 41.567 
    Info: ===================================================================
    Info: Node             : pll0|altpll_component|auto_generated|pll1|inclk[0]
    Info: Clock            : clk_12
    Info: Type             : High Pulse Width
    Info: 
    Info: Late Clock Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:      0.000      0.000           launch edge time
    Info:      0.000      0.000           source latency
    Info:      0.000      0.000           clk_12
    Info:      0.000      0.000 RR    IC  clk_12~input|i
    Info:      0.835      0.835 RR  CELL  clk_12~input|o
    Info:      2.910      2.075 RR    IC  pll0|altpll_component|auto_generated|pll1|inclk[0]
    Info: 
    Info: Early Clock Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     41.666     41.666           launch edge time
    Info:     41.666      0.000           source latency
    Info:     41.666      0.000           clk_12
    Info:     41.666      0.000 FF    IC  clk_12~input|i
    Info:     42.398      0.732 FF  CELL  clk_12~input|o
    Info:     44.366      1.968 FF    IC  pll0|altpll_component|auto_generated|pll1|inclk[0]
    Info:     44.477      0.111           clock pessimism
    Info: 
    Info: Required Width   :     0.000
    Info: Actual Width     :    41.567
    Info: Slack            :    41.567
    Info: ===================================================================
    Info: 
Info: Report Minimum Pulse Width: Found 1 results (0 violated).  Worst case slack is 63.542
    Info: Targets: [get_clocks {clk_T1}]
    Info: -nworst: 1
    Info: -detail: full_path
Info: Path #1: slack is 63.542 
    Info: ===================================================================
    Info: Node             : clk_T1
    Info: Clock            : clk_T1
    Info: Type             : Port Rate
    Info: Required Width   :     3.125
    Info: Actual Width     :    66.667
    Info: Slack            :    63.542
    Info: ===================================================================
    Info: 
Info: Analyzing Fast 1200mV 0C Model
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Deriving Clock Uncertainty
    Info: set_clock_uncertainty -rise_from [get_clocks {spi_sck}] -rise_to [get_clocks {spi_sck}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {spi_sck}] -fall_to [get_clocks {spi_sck}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {spi_sck}] -rise_to [get_clocks {spi_sck}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {spi_sck}] -fall_to [get_clocks {spi_sck}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {spi_sck}] -rise_to [get_clocks {spi_sck}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {spi_sck}] -fall_to [get_clocks {spi_sck}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {spi_sck}] -rise_to [get_clocks {spi_sck}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {spi_sck}] -fall_to [get_clocks {spi_sck}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.020
    Info: set_clock_uncertainty -rise_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.020
    Info: set_clock_uncertainty -fall_from [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.020
Info: Worst-case setup slack is 9.254
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     9.254         0.000 pll0|altpll_component|auto_generated|pll1|clk[1] 
    Info:    31.481         0.000 spi_sck 
Info: Worst-case hold slack is 0.035
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:     0.035         0.000 pll0|altpll_component|auto_generated|pll1|clk[1] 
    Info:     0.166         0.000 spi_sck 
Info: No Recovery paths to report
Info: No Removal paths to report
Info: Worst-case minimum pulse width slack is 10.165
    Info:     Slack End Point TNS Clock 
    Info: ========= ============= =====================
    Info:    10.165         0.000 pll0|altpll_component|auto_generated|pll1|clk[1] 
    Info:    16.454         0.000 spi_sck 
    Info:    41.622         0.000 clk_12 
    Info:    64.384         0.000 clk_T1 
Info: Report Timing: Found 1 setup paths (0 violated).  Worst case slack is 9.254
    Info: -to_clock [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}]
    Info: -setup
    Info: -stdout
Info: Path #1: Setup slack is 9.254 
    Info: ===================================================================
    Info: From Node    : frontend:front|spi_slave:arm|frame_done_n[1]
    Info: To Node      : frontend:front|spi_slave:arm|rx_addr
    Info: Launch Clock : pll0|altpll_component|auto_generated|pll1|clk[1] (INVERTED)
    Info: Latch Clock  : pll0|altpll_component|auto_generated|pll1|clk[1]
    Info: 
    Info: Data Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     11.417     11.417           launch edge time
    Info:     14.419      3.002  F        clock network delay
    Info:     14.524      0.105     uTco  frontend:front|spi_slave:arm|frame_done_n[1]
    Info:     14.524      0.000 FF  CELL  front|arm|frame_done_n[1]|q
    Info:     14.685      0.161 FF    IC  front|arm|rx_data[4]~1|datad
    Info:     14.748      0.063 FF  CELL  front|arm|rx_data[4]~1|combout
    Info:     15.119      0.371 FF    IC  front|arm|rx_addr~0|datac
    Info:     15.252      0.133 FF  CELL  front|arm|rx_addr~0|combout
    Info:     15.252      0.000 FF    IC  front|arm|rx_addr|d
    Info:     15.302      0.050 FF  CELL  frontend:front|spi_slave:arm|rx_addr
    Info: 
    Info: Data Required Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     21.834     21.834           latch edge time
    Info:     24.410      2.576  R        clock network delay
    Info:     24.569      0.159           clock pessimism
    Info:     24.549     -0.020           clock uncertainty
    Info:     24.556      0.007     uTsu  frontend:front|spi_slave:arm|rx_addr
    Info: 
    Info: Data Arrival Time  :    15.302
    Info: Data Required Time :    24.556
    Info: Slack              :     9.254 
    Info: ===================================================================
    Info: 
Info: Report Timing: Found 1 setup paths (0 violated).  Worst case slack is 31.481
    Info: -to_clock [get_clocks {spi_sck}]
    Info: -setup
    Info: -stdout
Info: Path #1: Setup slack is 31.481 
    Info: ===================================================================
    Info: From Node    : frontend:front|spi_slave:arm|last
    Info: To Node      : frontend:front|spi_slave:arm|miso
    Info: Launch Clock : spi_sck (INVERTED)
    Info: Latch Clock  : spi_sck (INVERTED)
    Info: 
    Info: Data Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     16.666     16.666           launch edge time
    Info:     18.123      1.457  F        clock network delay
    Info:     18.228      0.105     uTco  frontend:front|spi_slave:arm|last
    Info:     18.228      0.000 FF  CELL  front|arm|last|q
    Info:     18.692      0.464 FF    IC  front|arm|miso~SLOAD_MUX|datab
    Info:     18.850      0.158 FF  CELL  front|arm|miso~SLOAD_MUX|combout
    Info:     19.642      0.792 FF    IC  front|arm|miso|d
    Info:     19.836      0.194 FF  CELL  frontend:front|spi_slave:arm|miso
    Info: 
    Info: Data Required Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     49.999     49.999           latch edge time
    Info:     51.346      1.347  F        clock network delay
    Info:     51.377      0.031           clock pessimism
    Info:     51.357     -0.020           clock uncertainty
    Info:     51.317     -0.040     uTsu  frontend:front|spi_slave:arm|miso
    Info: 
    Info: Data Arrival Time  :    19.836
    Info: Data Required Time :    51.317
    Info: Slack              :    31.481 
    Info: ===================================================================
    Info: 
Info: Report Timing: Found 1 hold paths (0 violated).  Worst case slack is 0.035
    Info: -to_clock [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1]}]
    Info: -hold
    Info: -stdout
Info: Path #1: Hold slack is 0.035 
    Info: ===================================================================
    Info: From Node    : frontend:front|spi_slave:arm|rx_d_p[9]
    Info: To Node      : frontend:front|spi_slave:arm|rx_data[9]
    Info: Launch Clock : pll0|altpll_component|auto_generated|pll1|clk[1]
    Info: Latch Clock  : pll0|altpll_component|auto_generated|pll1|clk[1]
    Info: 
    Info: Data Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:      1.001      1.001           launch edge time
    Info:      3.584      2.583  R        clock network delay
    Info:      3.689      0.105     uTco  frontend:front|spi_slave:arm|rx_d_p[9]
    Info:      3.689      0.000 RR  CELL  front|arm|rx_d_p[9]|q
    Info:      3.865      0.176 RR    IC  front|arm|rx_data~10|datad
    Info:      3.930      0.065 RR  CELL  front|arm|rx_data~10|combout
    Info:      3.930      0.000 RR    IC  front|arm|rx_data[9]|d
    Info:      3.961      0.031 RR  CELL  frontend:front|spi_slave:arm|rx_data[9]
    Info: 
    Info: Data Required Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:      1.001      1.001           latch edge time
    Info:      3.981      2.980  R        clock network delay
    Info:      3.822     -0.159           clock pessimism
    Info:      3.842      0.020           clock uncertainty
    Info:      3.926      0.084      uTh  frontend:front|spi_slave:arm|rx_data[9]
    Info: 
    Info: Data Arrival Time  :     3.961
    Info: Data Required Time :     3.926
    Info: Slack              :     0.035 
    Info: ===================================================================
    Info: 
Info: Report Timing: Found 1 hold paths (0 violated).  Worst case slack is 0.166
    Info: -to_clock [get_clocks {spi_sck}]
    Info: -hold
    Info: -stdout
Info: Path #1: Hold slack is 0.166 
    Info: ===================================================================
    Info: From Node    : frontend:front|spi_slave:arm|frame[1]
    Info: To Node      : frontend:front|spi_slave:arm|frame[1]
    Info: Launch Clock : spi_sck (INVERTED)
    Info: Latch Clock  : spi_sck (INVERTED)
    Info: 
    Info: Data Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     16.666     16.666           launch edge time
    Info:     18.055      1.389  F        clock network delay
    Info:     18.160      0.105     uTco  frontend:front|spi_slave:arm|frame[1]
    Info:     18.160      0.000 RR  CELL  front|arm|frame[1]|q
    Info:     18.160      0.000 RR    IC  front|arm|frame[1]~0|datac
    Info:     18.331      0.171 RR  CELL  front|arm|frame[1]~0|combout
    Info:     18.331      0.000 RR    IC  front|arm|frame[1]|d
    Info:     18.362      0.031 RR  CELL  frontend:front|spi_slave:arm|frame[1]
    Info: 
    Info: Data Required Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     16.666     16.666           latch edge time
    Info:     18.123      1.457  F        clock network delay
    Info:     18.092     -0.031           clock pessimism
    Info:     18.112      0.020           clock uncertainty
    Info:     18.196      0.084      uTh  frontend:front|spi_slave:arm|frame[1]
    Info: 
    Info: Data Arrival Time  :    18.362
    Info: Data Required Time :    18.196
    Info: Slack              :     0.166 
    Info: ===================================================================
    Info: 
Info: Report Minimum Pulse Width: Found 1 results (0 violated).  Worst case slack is 10.165
    Info: Targets: [get_clocks {pll0|altpll_component|auto_generated|pll1|clk[1...]
    Info: -nworst: 1
    Info: -detail: full_path
Info: Path #1: slack is 10.165 
    Info: ===================================================================
    Info: Node             : frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a0~porta_address_reg0
    Info: Clock            : pll0|altpll_component|auto_generated|pll1|clk[1]
    Info: Type             : Low Pulse Width
    Info: 
    Info: Late Clock Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     11.417     11.417           launch edge time
    Info:     11.417      0.000           source latency
    Info:     11.417      0.000           clk_12
    Info:     11.417      0.000 RR    IC  clk_12~input|i
    Info:     11.900      0.483 RR  CELL  clk_12~input|o
    Info:     13.023      1.123 RR    IC  pll0|altpll_component|auto_generated|pll1|inclk[0]
    Info:     12.142     -0.881 RR  CELL  pll0|altpll_component|auto_generated|pll1|observablevcoout
    Info:     12.142      0.000 RR  CELL  pll0|altpll_component|auto_generated|pll1|clk[1]
    Info:     13.275      1.133 FF    IC  pll0|altpll_component|auto_generated|clk[1]~clkctrl|inclk[0]
    Info:     13.275      0.000 FF  CELL  pll0|altpll_component|auto_generated|clk[1]~clkctrl|outclk
    Info:     13.917      0.642 FF    IC  front|f3|fifo|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0|clk0
    Info:     14.405      0.488 FF  CELL  frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a0~porta_address_reg0
    Info: 
    Info: Early Clock Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     21.834     21.834           launch edge time
    Info:     21.834      0.000           source latency
    Info:     21.834      0.000           clk_12
    Info:     21.834      0.000 RR    IC  clk_12~input|i
    Info:     22.300      0.466 RR  CELL  clk_12~input|o
    Info:     23.378      1.078 RR    IC  pll0|altpll_component|auto_generated|pll1|inclk[0]
    Info:     22.456     -0.922 RR  CELL  pll0|altpll_component|auto_generated|pll1|observablevcoout
    Info:     22.456      0.000 RR  CELL  pll0|altpll_component|auto_generated|pll1|clk[1]
    Info:     23.548      1.092 RR    IC  pll0|altpll_component|auto_generated|clk[1]~clkctrl|inclk[0]
    Info:     23.548      0.000 RR  CELL  pll0|altpll_component|auto_generated|clk[1]~clkctrl|outclk
    Info:     24.152      0.604 RR    IC  front|f3|fifo|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0|clk0
    Info:     24.600      0.448 RR  CELL  frontend:front|packetfifo:f3|spififo:fifo|scfifo:scfifo_component|scfifo_t0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|ram_block1a0~porta_address_reg0
    Info:     24.800      0.200           clock pessimism
    Info: 
    Info: Required Width   :     0.230
    Info: Actual Width     :    10.395
    Info: Slack            :    10.165
    Info: ===================================================================
    Info: 
Info: Report Minimum Pulse Width: Found 1 results (0 violated).  Worst case slack is 16.454
    Info: Targets: [get_clocks {spi_sck}]
    Info: -nworst: 1
    Info: -detail: full_path
Info: Path #1: slack is 16.454 
    Info: ===================================================================
    Info: Node             : frontend:front|spi_slave:arm|rx_sr[0]
    Info: Clock            : spi_sck (INVERTED)
    Info: Type             : High Pulse Width
    Info: 
    Info: Late Clock Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     16.666     16.666           launch edge time
    Info:     16.666      0.000           source latency
    Info:     16.666      0.000           spi_sck
    Info:     16.666      0.000 FF    IC  spi_sck~input|i
    Info:     17.123      0.457 FF  CELL  spi_sck~input|o
    Info:     17.201      0.078 FF    IC  spi_sck~inputclkctrl|inclk[0]
    Info:     17.201      0.000 FF  CELL  spi_sck~inputclkctrl|outclk
    Info:     17.810      0.609 FF    IC  front|arm|rx_sr[0]|clk
    Info:     18.119      0.309 FR  CELL  frontend:front|spi_slave:arm|rx_sr[0]
    Info: 
    Info: Early Clock Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     33.333     33.333           launch edge time
    Info:     33.333      0.000           source latency
    Info:     33.333      0.000           spi_sck
    Info:     33.333      0.000 RR    IC  spi_sck~input|i
    Info:     33.780      0.447 RR  CELL  spi_sck~input|o
    Info:     33.867      0.087 RR    IC  spi_sck~inputclkctrl|inclk[0]
    Info:     33.867      0.000 RR  CELL  spi_sck~inputclkctrl|outclk
    Info:     34.442      0.575 RR    IC  front|arm|rx_sr[0]|clk
    Info:     34.721      0.279 RF  CELL  frontend:front|spi_slave:arm|rx_sr[0]
    Info:     34.789      0.068           clock pessimism
    Info: 
    Info: Required Width   :     0.216
    Info: Actual Width     :    16.670
    Info: Slack            :    16.454
    Info: ===================================================================
    Info: 
Info: Report Minimum Pulse Width: Found 1 results (0 violated).  Worst case slack is 41.622
    Info: Targets: [get_clocks {clk_12}]
    Info: -nworst: 1
    Info: -detail: full_path
Info: Path #1: slack is 41.622 
    Info: ===================================================================
    Info: Node             : pll0|altpll_component|auto_generated|pll1|clk[1]
    Info: Clock            : clk_12
    Info: Type             : High Pulse Width
    Info: 
    Info: Late Clock Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:      0.000      0.000           launch edge time
    Info:      0.000      0.000           source latency
    Info:      0.000      0.000           clk_12
    Info:      0.000      0.000 RR    IC  clk_12~input|i
    Info:      0.483      0.483 RR  CELL  clk_12~input|o
    Info:      1.606      1.123 RR    IC  pll0|altpll_component|auto_generated|pll1|inclk[0]
    Info:      0.725     -0.881 RR  CELL  pll0|altpll_component|auto_generated|pll1|observablevcoout
    Info:      0.725      0.000 RR  CELL  pll0|altpll_component|auto_generated|pll1|clk[1]
    Info: 
    Info: Early Clock Arrival Path:
    Info: 
    Info: Total (ns)  Incr (ns)     Type  Element
    Info: ==========  ========= ==  ====  ===================================
    Info:     41.666     41.666           launch edge time
    Info:     41.666      0.000           source latency
    Info:     41.666      0.000           clk_12
    Info:     41.666      0.000 FF    IC  clk_12~input|i
    Info:     42.104      0.438 FF  CELL  clk_12~input|o
    Info:     43.174      1.070 FF    IC  pll0|altpll_component|auto_generated|pll1|inclk[0]
    Info:     42.245     -0.929 FF  CELL  pll0|altpll_component|auto_generated|pll1|observablevcoout
    Info:     42.245      0.000 FF  CELL  pll0|altpll_component|auto_generated|pll1|clk[1]
    Info:     42.347      0.102           clock pessimism
    Info: 
    Info: Required Width   :     0.000
    Info: Actual Width     :    41.622
    Info: Slack            :    41.622
    Info: ===================================================================
    Info: 
Info: Report Minimum Pulse Width: Found 1 results (0 violated).  Worst case slack is 64.384
    Info: Targets: [get_clocks {clk_T1}]
    Info: -nworst: 1
    Info: -detail: full_path
Info: Path #1: slack is 64.384 
    Info: ===================================================================
    Info: Node             : clk_T1
    Info: Clock            : clk_T1
    Info: Type             : Port Rate
    Info: Required Width   :     2.283
    Info: Actual Width     :    66.667
    Info: Slack            :    64.384
    Info: ===================================================================
    Info: 
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 203 megabytes
    Info: Processing ended: Tue May 17 08:58:38 2011
    Info: Elapsed time: 00:00:08
    Info: Total CPU time (on all processors): 00:00:08


