Solar Orbiter EPD -- ICU to Kiel sensor communication protocol $Id: icu-message.txt 1466 2013-01-23 08:54:21Z stephan $ 0. Intro This document describes the communication between the ICU and the HEP/EPT or STEIN sensor units. 1. Command messages, ICU to Sensor 1.1 Format: Signaling: LVDS UART 115200 bps, 8 data, 1 stop bit, LSB first. Packet format: big endian, 6, 8, 10, or 14 bytes MSYNC, 16 bits: 0x3c3d SIZE 2 bits ADDR 14 bits DATA 0, 16, 32, 64 bits (SIZE=0, 1, 2, or 3) CRC 16 bits For most commands that expect data bits, if less bits are sent than expected, the sent value is padded with zeros. The CRC covers the whole packet: Polynom: x16 + x12 + x5 + x0 (See: http://www.ross.net/crc/download/crc_v3.txt) parameter NAME = "CRC-16/CITT"; parameter WIDTH = 16; parameter POLY = 'h 1021; parameter INIT = 'h ffff; parameter REFOUT = 0; parameter REFIN = 0; parameter XOROUT = 'h 0000; 1.2 Command address space ADDR 0x0000 master enables, strobes and resets ADDR 0x0004 PHA SRAM base/page address ADDR 0x0005 PHA SRAM page address ADDR 0x0006 PHA SRAM base/page address increment ADDR 0x0007 ENC SRAM base address ADDR 0x0008 MISC SRAM page address ADDR 0x0009 MISC SRAM page address increment ADDR 0x000a DUMP table page address ADDR 0x000b DUMP table page address increment ADDR 0x001X Register readback command ADDR 0x002X Data product clear command ADDR 0x003X Data product command ADDR 0x004X Memory scrubbing command ADDR 0x005X Memory readback command ADDR 0x0eeX EEPROM write ADDR 0x2600-0x26ff PPSS table write ADDR 0x2400-0x25ff L3Code table write ADDR 0x2800-0x2fff DP table write 1.3 Command details ADDR 0x0000 master enables, strobes and resets Telemetry: none Parameter: 64 bits [7:0] resets [15:8] various commands [23:16] enable commands [31:24] disable commands [47:32] more enables [63:48] more disables Description: Each bit in the parameter word is assign an action that is executed when the bit is set. [0]: abort, reset engines that produce telemetry [1]: reset modulus, next pps restarts the 1h cadence cycle [2]: stop pps scheduler [7]: reset errors register [8]: clear PHA buffers [9]: stop L3 processor [10]: clear counters [11]: toggle PHA buffer base [15]: issue a PPS enable/disable [16]/[24]: accept event from frontend [17]/[25]: l3 event processing [18]/[26]: PHA data storage [19]/[27]: set/reset histogram base address MSB [20]/[28]: [21]/[29]: [22]/[30]: PPS execution from command message [23]/[31]: PPS execution from 1HZ signal ADDR 0x0004 PHA SRAM base/page address ADDR 0x0005 PHA SRAM page address ADDR 0x0006 PHA SRAM base/page address increment Telemetry: none Parameter: 19 bits [18:12] base address [11:0] readout page address Description: Configure the PHA storage address. ADDR 0x0004 Set both base and page. ADDR 0x0005 Set only the readout page. ADDR 0x0006 Increment base and/or page without carry between page and base Usage: ADDR 0x0004: Initial configuration. ADDR 0x0005: Reset readback page at the start of a PHA acquisition cycle. ADDR 0x0006: advance readback page address during a readback cycle. ADDR 0x0006: toggle page MSB between PHA acquisition cycles. Memory readback relative to the PHA base/page address is selected by the dump address 0xA40xxx. The address given in the command is added to the page, but not the base address. Bit [18] is xor-ed to the base address MSB, to select the buffers not currently being accumulated. ADDR 0x0007 ENC SRAM base address Telemetry: none Parameter: 6 bits [18:13] Encoder acc base address. Description: Configure the encoder accumulator address. Usage: Initial configuration. The data encoder needs 8k words of SRAM. This register configures the base address of that memory area within the external SRAM. ADDR 0x0008 MISC SRAM page address ADDR 0x0009 MISC SRAM page address increment Telemetry: none Parameter: 18/36 bits [18:0] readback address [50:32] prefix mask (for increment only) Description: Configure the address for miscellaneous memory readback. ADDR 0x0008: Set the misc page address ADDR 0x0009: Increment the address, but keep the masked bits unchanged. The memory dump command can read any memory address without the help of a page address. But for periodic readback cycles of largish blocks of memory in small chunks a page address can be used. A periodic command will dump some words relative to the page, then increment the page by the size transfered. The increment shall wrap around when the end of the block is reached. Memory readback relative to the misc page address is selected by the dump address 0xBxxxxx (SRAM) or 0xFxxxxx (EEPROM). The address given in the command is added to the misc page address. Usage: Diagnosics. ADDR 0x000a DUMP table page address ADDR 0x000b DUMP table page address increment Telemetry: none Parameter: 12/48 bits [11:0] address [27:16] increment mask (for increment only) [43:32] old prefix mask (for increment only) [59:48] new prefix (for increment only) Description: Configure the address for congfiguration table readback. Page address for configuration table readback. These are stored in the FPGA, pps schedule table, data products table, and L3 trigger opcodes. ADDR 0x000a: Set the page address. ADDR 0x000b: Increment the page address. The Increment command keeps the bits masked by [43:32], increments the bits not masked by [27:16], and sets the bits from [59:48]. Usage: Dribble of the config memories. ADDR 0x001X Register readback command Telemetry: Paket APID 1X, data size 2..130 bytes Parameter: 16 bits. [15:0]: register select mask Description: Read up to 16 words of register bits. Each bit in the select mask enables the readback of a register. For each set bit, a 64-bit word will be put into the telemetry packet. The data is preceeded by the select mask in the first two data bytes of the packet. Readback registers: 0: Status register [7:0] error bits [15:8] frontend state bits [23:16] enables [47:32] more enables 1: base/page adresses [11:0] PHA page [18:12] PHA base [24:19] encoding base [43:25] misc page [57:44] dump page 2: clock [23:0] usecond [35:24] modulus counter [38:36] modulus [39] pps scheduler is idle Error bits: [0] internal RAM SEU error [1] internal RAM single bit error [2] external SRAM SEU error [3] external SRAM single bit error Usage: diagnostics, housekeeping ADDR 0x002X Data product clear command ADDR 0x003X Data product command Telemetry: Paket APID 3X, data size variable Parameter: 23 bits [11:0] number of data products to be processed [34:24] start entry in the DP table Description: trigger the data product scheduler into action ADDR 0x0020 Execute the data products without generating a telemetry packet. ADDR 0x003X Generate a telemetry packet from the specified data products. Usage: Periodically from the PPS scheduler. ADDR 0x0020 can be used to call some data product table entries which only clear the histogram space in preparation for the next acquisition cycle. ADDR 0x004X Memory scrubbing command ADDR 0x005X Memory readback command Telemetry: Paket APID 5X, data size variable Parameter: 36 bits [23:0] memory start address [35:24] number memory words to read Description: Trigger the data product scheduler into action. ADDR 0x004X: read the specified memory words without generating a telemetry packet. ADDR 0x005X: Generate a telemetry packet containing the specified memory contents. The memory address ranges are: internal RAM readback 0x0c2aaa l3code readbacks 0x2c2aaa l3code dump_page 0x0800aa counters 0x2800aa counters dump_page frontend memory 0x4saaaa frontend readbacks 0x6saaaa frontend dump_page external memory readback 0x8aaaaa SRAM 0x9aaaaa SRAM HIST page 0xAaaaaa SRAM PHA page 0xBaaaaa SRAM MISC page 0xCaaaaa EEPROM 0xDaaaaa EEPROM 0xEaaaaa EEPROM MISC page 0xFaaaaa EEPROM MISC page a[23]==1: external memory a[22]==0: SRAM a[22]==1: EEPROM a[23]==0: FPGA memory resources a[21:20]: word size 1/2/4/8 bytes a[22]==0: backend resources a[22]==1: frontend resources This engine produces telemetry packets filled with data read from memories. The address and size of the meory region is send in the first four data bytes, followed by the memory contents. Usage: ADDR 0x0040: EDAC scrubbing of internal memories. ADDR 0x005X: p=0x2c2000 config table dribble ADDR 0x005X: p=0x082000 counter telemetry ADDR 0x005X: p=0xA40000 PHA telemetry ADDR 0x005X: p=0xF00000 EEPROM readout ADDR 0x0eeX EEPROM write Telemetry: none Parameter: SIZE==3 : 64 bit [63:0] data bytes, big endian Parameter: SIZE==2 : 24 bit [16:0] byte address in the EEPROM [30:24] number of bytes to be written. Description: Write a page of EEPROM data. The data is loaded into a RAM page of 128 bytes. A command with SIZE==3 loads 8 bytes into the page RAM in the FPGA at the address specified by the four LSB of the command ADDR. A command with SIZE==2 triggers the page write operation for a range of consequtive bytes within the page. The data must be loaded at the offset within the RAM page that it shall be written to the EEPROM, i.e., 7 LSB of the address must match. The page address may wrap around, so that some bytes at the end and some bytes at the start of the page will be written. If the number of bytes is larger or equal to 128 the whole page will be written. ADDR 0x2600-0x26ff PPSS table write ADDR 0x2400-0x25ff L3Code table write ADDR 0x2800-0x2fff DP table write Telemetry: none Parameter: 64 bits [63:0] data word Description: write a word (64bits) into a configuration table inside the FPGA. 128 entries in the PPS scheduler of 128 bits occupy 256 words of 64 bits in the table memory. 4x256 L3 trigger opcodes of 32 bits occupy 512 words in of table memory. 2048 entries in the data products table of 64 bit occupy as manny words in the table memory. These memories are physically 72-bits wide, with 8 bits used for EDAC Hamming codes. The Hamming codes will be generated when a word is written. When a single bit error is detected during a read, the corrected word will be written back into the table memory. To periodically scrub the memories a command ADDR 0x0040 can be used, but the forseen usage pattern ensures that each data word in use will be read at least once per second anyway. 2. Telemetry packets 2.1: Format Signaling: LVDS UART 115200 bps, 8 data, 1 stop bit, LSB first. Packet format: big endian, ITF packets as defined by Chan TSYNC 32 bit = 0xbebacafe FLAGS 3 bit = 0 SIZE 13 bit = n+4 APID 16 bit DATA n bytes CRC 16 bit = CRC-16/CITT, see above A telemetry packet is sent in response to a command message. The command message my be received from the ICU or the PPS scheduler. The PPS may be issued by a command message or by the 1Hz signal from the ICU. The sensor can operate autonomously by including a PPS commad as the last entry in the PPS schedule table, thus triggering itself periodically. The sensor can operate without any autonomous scheduler by issuing all actions explicitly via a command. 2.2. Packet mode Not all command messages lead to a response. All commands that cause a telemetry packet to be issued do not parse the four LSB of the command ADDR. Those bits are copied into the four LSB of the packet APID. I.e., each telemetry packet is flagged with four bits in the APID. These flags shall be used by the ICU to decide how to process the packet. 16 different packet modes may be defined, e.g., 0: Miscellaneous, ignored 1: Miscellaneous, dignostics 2: Miscellaneous, scheduled 3: Miscellaneous, high priority 4: PHA telemetry 5: HK telemetry 6: Burst mode criteria counters 7: Slow control, temperatures 8: Nominal science telemetry 9: Additional science telemetry for EPD burst mode 10: Additional science telemetry for HET burst mode 11: Additional science telemetry for SWAVES triggered burst mode 12-15: spare science telemetry modes. The ICU shall maintain a mask telling which packet shall be processed and/or sent in telemetry. Paket modes 0..3, if enabled, shall be individually wrapped in a telemery packet and sent as a MISC packet to ground. Packet mode 4: The ICU shall collect a sequence of PHA packets into larger PHA telemetry packets to save packaging overhead. The ICU shall truncate PHA packets if the APID and Header matches a PHA page memory dump. The first word in the packet indicate the size of valid data in the packet. The data shall be send with the ITF APID. Packet mode 5: The ICU shall collect a sequence of HK packets into larger PHA telemetry packets to save packaging overhead, and to collect various data items into a common data structure. All IFT packets shall be copied with APID and all data. Packet mode 6: The ICU shall parse the data inside these packets to decide if the sensor shall flag a burst mode. Packet mode 7: The ICU shall parse these packets to read sensor status. The ICU shall use temperature data from these packets to control the sensors operational heater. Packet mode 8-15: The ICU shall collect ITF packets of this mode into buffers, one buffer for each mode. The data shall be copied without APID. When a buffer is full, if shall be replaced by an empty buffer. The full buffer shall be queued for telemetry if the necessary burst mode conditions are met. If the burst mode conditions are not met, the buffer may be kept in a ring of pending buffers until a new buffer is required and no unused buffers are available. Alternativley, one buffer of each mode is kept in addition to the one being filled. When burst mode is triggered, the pending buffers shall be considered again for telemetry, so that some data leading up to the burst mode becomes available for analysis on the ground. The mask for MISC mode processing shall expand to all 16 packet modes, so that all packet modes can be selected for MISC mode processing. This may be applied to spare science modes if the need arises, or for diagnostics of the other packet types. Those packets will be send as MISC packets in addition to the normal processing, if applicable. Packet mode 0 shall not normally enabled. Packets of that mode shall be ignored by the ICU. 2.3 Packet types, APID The first 16 bits of the ITF packet payload is the APID of the packet. The remaining payload is the packet DATA. The DATA maye include a data header. The APID normally corresponds to the ADDR of the command that generated the packet, with the last four bits being the packet mode. APID 0x001X: register readback DATA header: 16-bit, register mask DATA: see command ADDR 0x001X APID 0x003X: data products DATA header: 3-bit, modulus DATA: compressed and/or uncompressed science counters APID 0x005X: memory readout DATA header: 32 bits, [31:24] size and [23:0] address DATA: memory words 3. Frontend The addresses and resources described above are implemented in a common backend module. They work the same for STEIN and HET/EPT. The frontends will implement sensor-specific commands and packet types. * enables, resets, * readback registers, error bits, * commands, * memory dump address ranges, * housekeeping ADC readout packets. 3.1. HET/EPT TODO: 3.2. STEIN TODO: 4. Packet reception in the ICU The telemetry packets from the sensor arrive somewhat indeterministically within the one-second acquisition period, some packets in every second, others at longer intervals. The ICU shall not ever expect any packets, instead it shall operate on the packets received. A monitoring task may flag periods where the number and/or type of packages deviates from the expectations, but the processing shall not depend on expectations. About once per second the ICU shall look into the UART receiver ring buffer and parse any valid packets received, i.e., it must find a packet header, reasonable packet length, and a valid crc checksum. The packets shall be copied out of the ring buffer and queued for processing. If data is received that is not valid, the receiver shall be flagged to be ignored by the fast processing thread, and a low priority thread shall search for packet TSYNC words and matching CRC, discarding bytes as it goes. The search must start behind the SYNC word of the invalid packet, not after the invalid CRC. All packets found shall be copied and queued and the receiver flagged active again for fast thread processing. 5. Configuration table formats The backend operates from three configuration tables stored in EDAC protected embedded SRAM blocks within the FPGA. The table memory words are 64-bits wide, stored in 72-bit wide memories, with 8 Hamming code bits added. A single bit error will be detected on any read and corrected, both as returned by the read and in the memory. The tables are written by 64-words via command messages. The table users require 32, 64, or 128 bit words, the required (de-)multiplexing from the 64-bit read bus is handled in the respective module. 5.1. Pulse Per Second Scheduler The PPSS runs from a table with 128 entries, with 128 bits per entry. When a PPS is received and enabled, the entries in the table are considered in sequence for a µsecond time match. When the time matches, the entry is checked for a cadence modulus match, and executed when a match is found. The scheduler then proceeds to the next table entry. The table entries are stored in two consecutive words of table memory, big endien. The table memory is 256 words deep. The µsecond match column shall be ordered monotonously in the table, otherwise the offending entry will not match again before the next PPS, or the µsecond counter wraps. The scheduler can match and exectute at most one command per µs. The µsecond counter is 24-bit wide, i.e., it wraps after 16.77 seconds. The counter is reset when a PPS is received and enabled. The modulus is generated by a cascade of counters which increment when a PPS is received and enabled. The counters count periods of 5, 2, 3, 2, 5, 2, and 6 ticks. Each counter increments when all preceeding counters reached their period. The modulus is a three bit value identifying the number of counters that wrapped with the last PPS. The result is a cascade of cadences with periods of 1, 5, 10, 30, 60, 300, 600, and 3600 seconds. The modulus sequence starts 0,0,0,0,1,0,0,0,0,2,0,0,0,0,1,0,0,0,0,2,0,0,0,0,1,0,0,0,0,3,0,0 ... The data products engine will produce variable sized science data packets, where the number of generated data products depends on the modulus. Higher moduli will always contain all data present in lower moduli, and some that only come at the higher cadence. Each PPSS table entry may require a match to any subset of cadence counters. The format of the table entry is [63:0] command DATA [79:78] command SIZE [77:64] command ADDR [103:80] modulus match [127:104] µsecond match At a µsecond match the scheduler proceeds to the next entry. When both the µsecond and the modulus match, the command message is issued. The command SIZE is not enforced, i.e., no check is made that data bits beyond the indicated SIZE are zero. The modulus match has three parts: [95:80] cadence match values [96] enable a match every second if no other match was selected. [103:97] select which cadence counters must match When none of the bits [103:96] are set, the entry is disabled. The cadence counters are different length, so the mapping of match value bits to counters is a bit irregular [82:80] counter 1, 1 second increment, 5-seconds cadence [83] counter 2, 5 seconds increment, 10 seconds cadence [85:84] counter 3, 10 seconds increment, 30 seconds cadence [86] counter 4, 30 seconds increment, 60 seconds cadence [89:87] counter 5, 60 seconds increment, 300 seconds cadence [90] counter 6, 300 seconds increment, 600 seconds cadence [93:91] counter 7, 600 seconds increment, 3600 seconds cadence [95:94] unused, spares, may be needed if a differnt cadence sequence is implemented. The PPSS can stop itself, restart itself, can modify its own configuration table, all by issuing the respective commands at apropriate times. The last used table entry should be a PPSS stop command, to avoid a rerstart when the PPS fail to arrive. Or the PPSS shall restart itself after one second, to run independent from the ICU 1Hz signal. Self modification can be used if something shall be done an irregular number of times per cadence. E.g., send 16 HK packets per hour. The PPSS could enable the relevant command at the beginnig of the hour and disable it after it has run 16 times. Another self-modifiy use is to schedule EEPROM page writes at the end of a second. Those page writes may be necessary during nominal data taking, but they shall not interfere with the memory load during the acquisition cycle. To avoid interference those writes shall be scheduled at the end of a second by the PPSS. The ICU will write the necessary entries into the table, which includes a command that truncates the table to the previous state after the EEPROM page write was issued. Or the table may include a entry that is reserved for ICU issued run-once commands, followd by an entry that disables the previous entry. That mechanism can be used to request diagnostic telemtry packets without interfereing with nominal telemetry. 5.2. Data products scheduler. Data products are defined by the entries in the DP table. Each 64-bit word defines one histogram sum and how is shall be processed. Each data product entry is associated with a scratch space in external memory for accumulation of counts over multiple acquisition periods. The data products will be summed and processed in sequence from the table and the results packed into a telemetry packet. The command message that triggers the engine specifies the start address within the table and the number of entries to process. The table is 2048 entries deep. Each entry defines a region in histogram memory that shall be summed. When the sum is ready, it can be submitted to the encoder engine or just left in the accumulator for the next data product entry to be added to it. That way irregularly shaped histogram windows can be defined. A sum that is submitted to the encoding engine can be further accumulated in the scratch memory for one of the 8 cadence periods. When the period is complete, the accumulated sum is either floating point encoded or compressed in a lossy variable length format. The resulting bits are transfered into a fifo. When the specified number of data products were processed and the size of the data volume is known, the fifo contents will be formated for telemetry. There are two sources for variability of the packet size: depending on the cadence modulus there will be a variable number of sums ready for transmission, and when compression is employed, each sum will require a vaiable number of bits depending on the value. The format of the data product table enties is: [17:0] Histogram window address [21] Flag ADD: do not clear the accumulator at the start of the sum. [22] Flag TELE: submit the sum to the encoder. [23] Flag CLEAR: zero the histogram, memory after read. [26:24] Cadence sum modulus. [30:28] Encoding length modulus. [39:32] Number of bins in x to add minus one. [47:40] Number of bins in y to add minus one. [63:48] Stride of the y-bins in memory. The x-bins are read from consecutive addresses in the histogram memory. The y-stride is added to the address of the last last x-bin to reach the first x-bin in the next row. If data is accumulated into a 2-dimensional histogram with 256x256 bins, stored in a continuous memory region at address A, and a rectangular window with NX*NY bins shall be summed, with the lower left corner in bin (AX,AY), the window parameters need to [17:0] = A + AX + 256*AY [39:32] = NX-1 [47:40] = NY-1 [63:48] = 256-NX+1 The cadence sum modulus specifies that the data shall be accumulated for 1, 5, 10, 30, 60, 300, 600, 3600 seconds. If bits [26:24] are zero, the window sum is submitted for telemetry every second. Otherwise it is apropriately acumulated in the scratch space. When the encoding length modulus specification is larger than the cadence sum modulus, the accumulated sums will be compressed into streams for periods corresponding to the specified cadence. In that mode only the first sum will be transmitted in high resolution, all following sums will be encoded as the difference to the number that has been as the previous count. I.e., when the stream is decoded, each value needs to be added to previous count result to obtain the next result. Since the compression is lossy, the encoder needs to keeps track of what has been sent, so that the differences can be calculated towards what the receiver reconstructs as the previous count rate, not the real prevoius count rate. At the end of the stream, the residual will be encoded and sent as an additional data item, so that precice values can be obtained at longer cadence periods in low rate conditions. When the encoding length modulus is smaller or equal to the cadence sum modulus, the sums will be converted to 16-bit floating point numbers. These will not be aligned to byte boundaries even when the packet only consists of uncompressed values, because the 3-bit modulus is prepended to the data product bits in the packet. For irregularly shaped windows series of data product entries is summed. All but the first nned to set the ADD flag, so that the new sum is added to the previous sum. The last entry sets the TELE flag to submit the final sum to the encoder. When the sub-windows overlap, the early entries shall set the CLEAR flag, so that the later overlapping sub-windows find zeros in those bins that were already counted. This requires that there are no other data products that include bins from those sub-windows. 5.3. Level 3 trigger code. The L3 trigger excutes instructions with a constant size of 32 bits, with two consecutive instructions stored big endian in each table memory word. The instruction memory is logically organized as four banks of 256 instructions each, for a total of 1024 instructions. Each instructions stores a result in a registerfile with 256 registers, at the address that is the same as the instruction address within the bank. The register file keeps the results of all previous instructions available, as long the instructions are executed sequentially. There are no flow-control instructions, except for a simple, inefficient goto. Most code shall employ conditional execution for simple flow control. Condition codes can be set with comparisson or bit-test instructions. The goto can target a different bank. Before the L3 trigger executes, the PHA amplitudes and auxiliary data is stored in the last 32 registers of the register file. Those get overwritten when the processor executes the last 32 instructions in a bank, but by that time the data should have been calibrated and saved in earlier registers. Which of the four code banks is executed depends on the event class derived by the L2 trigger. The instruction format is [31:30] The two MSB are the condition code cc=01: unconditional cc=11: execute if condition bit is true cc=10: execute if condition bit is false cc=00: reserved [29:24] Up to six bits define the opcode [28:0] Up to 29 command parameters [7:0] x-register address [23:16] y-register address [11:8] x-register shift [15:12] y-register shift [29:8] signed immediate constant (ADDI) [15:8] unsigned immediate constant u (TRIM, COMP) [23:16] unsigned immediate constant v (TRIM) [23:8] unsigned immediate constant (PHA) [26:24] comparisson opcode Opcodes TODO: This table needs update cc1i iiii iiii iiii iiii iiii xxxx xxxx ADDI Rx + i21 cc00 1000 yyyy yyyy jjjj iiii xxxx xxxx ADD ( Rx >> i4 ) + (Ry >> j4) cc00 1001 yyyy yyyy jjjj iiii xxxx xxxx SUB ( Rx >> i4 ) - (Ry >> j4) cc00 1110 vvvv uuuu uuuu uuuu xxxx xxxx MULI (Rx * u12) >> 4 cc00 0001 ---- ---- ---- ---- xxxx xxxx LOG log_2(Rx) cc01 0ttt yyyy yyyy uuuu uuuu xxxx xxxx CMP1 Rx + u8 <=> Ry cc01 1ttt yyyy yyyy uuuu uuuu xxxx xxxx CMP2 Rx <=> Ry + u8 cc00 1010 vvvv vvvv uuuu uuuu xxxx xxxx TRIM max(min(Rx, u8), v8) cc00 1011 uuuu uuuu uuuu uuuu xxxx xxxx PHA Rx + u16 cc00 110- yyyy yyyy ---u uuuu xxxx xxxx HIST Rx + (Ry << u5) cc00 0000 ---- ---- ---- ---- ---- ---- STOP BTST Rx[u5] ^ n GOTO u10 proposal ttt==000: == ttt==000: 0 ttt==001: != ttt==001: > ttt==100: <= ttt==010: == ttt==110: >= ttt==011: >= ttt==111: < ttt==100: < ttt==101: > ttt==101: != ttt==110: <= ttt==111: 1 The output of the L3 trigger are issued by the PHA and HIST instructions, which instruct the PHA record to be saved in the PHA buffer memory, and increment a histogram bin, respectively.